( ESNUG 555 Item 5 ) -------------------------------------------- [01/22/16]
Subject: Sanjiv on MENT Veloce, Ansys PowerArtist, and FinFET power issues
DAC'15 Troublemakers Panel in San Francisco, CA
Cooley: Ok. Sanjiv. You're friends with Mentor. You're tight with
Mentor. Yet when it came time to buy a RTL power tool or
team up with an RTL power tool, Mentor Veloce teamed up with
Ansys not you in RTL power estimation. Why?
Sanjiv: It's called being customer driven. One, I think, the Veloce
Ansys integration is an open one. There can be multiple RTL
power analysis tools becoming part of that, including ours.
This first tool was driven by a particular customer who wanted
a particular integration and so we've been talking to the
Veloce team. We're working with the Veloce team and they
said that's the first integration and that's exactly what
happened.
Cooley: So it was a customer that was driving it?
Sanjiv: One customer who has and who's using a PowerArtist and uses
Veloce and wanted to see the two of them to work together.
Cooley: Do you see... OK, I'll be honest here. What's the difference
between these three tools? I mean RTL power optimization
pretty much is a wash. You guys are pretty much getting the
same numbers...
Sanjiv: No, when you look at it, most people who are looking at RTL
level power have been using power analysis tools. And in power
analysis, I think there is a big change coming with FinFET
designs. The kind of technologies that worked in the past,
were given adequate power numbers at RTL level...
Cooley: Wait a minute, wait a minute. RTL level analysis for
FinFET is different?
Sanjiv: Yes it is. If you would look at what's going on with FinFET
the dynamic power becomes a much large portion of the power.
And until FinFET, leakage power was almost as big as dynamic
power. And so if you were able to estimate the dynamic power
within a certain level of accuracy, your overall accuracy
would be still OK.
But now when the leakage power comes down dramatically and the
dynamic power is now a much bigger proportion, the accuracy of
your RTL power analysis tools has to get much, much better.
And so that's one area that they're going through a big change.
The area that Calypto has been good at has been power
optimization at the RTL level. That's an area that we feel
really good about technology. We don't lose benchmarks doing
the RTL level power optimization.
But the true challenge for dynamic power, for FinFET design, is
that because the dynamic power is becoming such a large portion
of the overall power, you need to give designers (because today
right now power experts are doing a lot of the optimization) a
lot of the analysis.
What you have to do is to give RTL designers the tools to be
able to iterate and try different micro-architectures and
different RTL configurations -- and be able to get their RTL
power down. And that's where we the market is going right now.
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