( ESNUG 546 Item 1 ) -------------------------------------------- [01/15/15]
Subject: A surly Martin Lund schools Cooley on Cadence IP/VIP/memory-IP
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OOPS!: An embarassing IP side story started 30 months ago at CDNLive'12,
when Lip-Bu Tan had announced that he appointed Martin Lund from Broadcom
to be his SVP for all CDNS IP.
"Lund's primary focus is to expand the Cadence design IP portfolio"
- Cadence press release (03/05/12)
The embarrassment is two part: first, 2 years later Martin Lund skipped
the CDNLive'14 meeting -- and second, barely any engineers at DAC'14 had
mentioned Cadence IP whatsoever. Said numerically: out of the 93 total
user comments on IP only 3 were on Cadence IP -- and they were 2 minor
Denali Memory IP cites and one Verisity Specman "e" VIP cite. OUCH!!!
- from http://www.deepchip.com/items/dac14-06.html |
From: [ Martin Lund of Cadence ]
Hi, John,
I think your report is way off from reality.
I personally met with many customers at DAC. Maybe they aren't on your
email list, or they work at one of our customers who are very sensitive
about info leaks. I was at DAC'14 and on the DAC IP panel -- but I did
not see you there. Did you even attend the show? You shouldn't skip
IP events if you want to credibly cover IP on DeepChip.
 
Yes, it's true that I missed CDNLive Silicon Valley last year. I was in China
meeting with HiSilicon. You may have read about their licensing our DDR IP.
China is HOT for IP! But many Asian companies and engineers aren't yet
comfortable with sharing info with strangers over email, or disclosing info
on social media sites.
I am planning to attend CDNLive'15 San Jose, so don't be a stranger. Come
see the IP Track and talk to the presenters and participants.
There's a lot more happening with Cadence IP that was not represented in
your DAC IP report. For example I just got back from CES 2015 and I really
think you should have been there. It was bursting with product decision
makers, executives, and Designers and Architects looking for IP to help them
differentiate and get to market faster.
At CES we had 3 meeting rooms fully booked for 3 solid days.
If you had gone to CES'15, John, you'd have seen many consumer
electronic products there with Cadence IP in it. Some products you might
have to guess about, because those customers are notoriously secretive and
we can't divulge that our IP is in their products. A few customers even
go so far as to require that we use code names for all internal meetings,
email, and documents.
 
Our Tensilica IP was huge at CES'15: over 50 top tier semi companies and
system OEMs use our HiFi DSPs. We demoed our IVP image/video processor IP
with breakthrough energy efficiency and performance. Tensilica has 100's
of design wins, and over 1000 different processor cores in full production
silicon. Our Tensilica DSPs compliment ARM's processors -- which we see
in most of the SoCs our customers build and ship. Our Tensilica portfolio
has: embedded controllers and microcontrollers, audio DSPs, video DSPs,
imaging DSPs, communications DSPs, network processors (NPUs); security
processors -- and wide range of proprietary instruction set processors
created by our customers.
 
Our team will also be at Mobile World Congress -- another fantastic IP show.
Are you going to attend? This where our IP customers hang out. Same goes
for the Memcon event in the fall, which is the only event for DDR and other
memory IP. It's a big deal, Memcon. We're planning some cool things for
that show -- don't miss it!
---- ---- ---- ---- ---- ---- ----
John: since you seem so disconnected on what I do, let me school you on the
Cadence IP which I manage:
- Our VIP business leads the industry. It's used by over 500 companies
around the world. With simulation VIP for over 40 protocols. And
knowing how you distrust "vague EDA vendor claims", here they are:
ARM AMBA 5 CHI, AMBA 4 ACE, AXI 3/4, AHB, APB, AMBA 4 Stream, CAN,
Display Port, Ethernet 10/100/1G/10G, Ethernet 25G/50G, Ethernet
40G/100G, HDMI 1.4, HDMI 2.0, I2C, JTAG/cJTAG, LIN, MHL 3.0, MIPI
CSI-2, MIPI CSI-3, MIPI C-PHY, MIPI DigRF, MIPI D-PHY, MIPI DSI,
MIPI LLI 2.0, MIPI M-PHY, MIPI SLIMbus, MIPI Sound Wire, MIPI UniPro,
NVM Express, OCP 2.2, OCP 3.0, PCI, PCIe Gen2, PCIe Gen3, PCIe Gen4,
PCIe SR-IOV, PCIe MR-IOV, M-PCIe, PLB 6, SAS 6G, SAS 12G, SATA 3G/6G,
SRIO 2.1, SRIO 3.0, UART, USB 2.0 w/ OTG, USB 3.0 w/OTG, USB SSIC.
And, yes, our VIP runs in Incisive, Synopsys VCS, and MENT Questa
- For hard IP, a good example is our PCI Express offering: PCIe Gen1,
Gen2, and Gen3, both controllers and PHYs. Root point, End point,
and Dual mode are also provided, as is M-PCIe. We have built our
PHYs to be multi-protocol and multi-lane.
The other protocols we offer for hard IP: USB 2, USB 3, USB OTG,
SSIC, HSCI, MIPI D-PHY, MIPI M-PHY, CSI-2, DSI, UniPro 1.6,
DigRF v4/BIF, and MIPI SoundWire/SlimBUS. And Ethernet 100G MAC,
40G/10G MAC, 1G MAC, 10/100 MAC, 10G-KR, 1G PHY, XAUI/RXAUI, and
SGMII/QSGMII.
I heard just this week we have somewhere near 400 hard IP datasheets.
- For hard memory IP, our Denali group supplies DDR 2/3, LPDDR 2/3 PHYS
and controllers, are a leader in DDR4 and LPDDR4, and offer a unique
product that combines DDR4, DDR3, LPDDR4, LPDDR3 in a multi-protocol
PHY IP. Other hard memory IP we offer: ONFi 1/2/3 IP, Toggle 2/1,
UFS 2.0, SD/SDIO, eMMC, UHS, Wide I/O, and HMC 15Gbps.
- For memory models our VIP Catalog has 6500 vendor-certified memory
models across more than 60 protocols: Cellular SRAM, Compact FLASH,
DDR DIMM, DDR SDRAM, DDR Sync GFX RAM, DDR Sync RAM, DDR2, DDR3,
DDR4 Incl. 3DS, DDR4 LRDIMM, DDR4 SDRAM, Delay line, DFI, Embedded
SSRAM, Embed. SSRAM TI, eMMC 4.4, eMMC 4.5, eMMC 5.0, Enhanced SDRAM,
FCRAM, FIFO, FLASH (basic), FLASH ONFi, Flash ONFi 3/4, FLASH PPN DDR,
FLASH Toggle NAND, FLASH Toggle NAND 2, GDDR2, GDDR3, GDDR4, HBM,
HMC, LBA NAND, LL DRAM, LPDDR, LPDDR2, LPDDR3, LPDDR4, LR DIMM,
Memory Stick, Memory Stick Pro, NAND FLASH, NOR FLASH Spansion,
One NAND FLASH, PROM, Pseudo Burst SRAM, QDR SRAM, Rambus DRAM, Rambus
Turbo Mode, Register File, RL DRAM, Scratch pad, SD Card, SD Card 3.0,
SD Card 4.0, SDIO, Synch DRAM, Synch Mask ROM, Synch RAM NEC, UFS 1.0,
UFS 2.0, Wide I/O, Wide I/O 2.
Our best kept secret is our analog portfolio of ADC and DAC parts. Since we
make Virtuoso and ADE, we have world class analog designers who have spent
decades creating the highest speed, and best performing -- think analog noise
robustness and signal strength -- IP in the industry. (This is why our DDR
and Interface PHYs are so high speed and robust in performance.) It is also
why our Analog IP seems to attract some of the best customers in the world.
The full list of our Analog IP is very long but it includes the WiGig/Wifi
Analog Front End (AFE), LTE AFE, ADC/DAC AFE, PLL, and DLL. There is also
analog SoC system IP for temperature monitoring, voltage monitoring, PVT
monitoring, Power Management, and MP SerDes.
---- ---- ---- ---- ---- ---- ----
Our IP Group had record revenue for Q3 2014. We made up 11% of Cadence's
revenue overall.
And in case you missed it, Gartner reported that in 2013 Cadence came in 4th
in the overall IP market and grew at 163% -- which is much faster growth than
the overall IP industry.
In summary, John, you're missing out on what's really happening in IP. We
already lead in memory and VIP; Tensilica is growing like crazy and we are
the one to watch in standards-based IP.
- Martin Lund
Cadence Design Systems, Inc. San Jose, CA
---- ---- ---- ---- ---- ---- ----
Related Articles:
ARM, Synopsys DesignWare, Mentor VIP, plus Cadence IP went missing?
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