( ESNUG 514 Item 1 ) -------------------------------------------- [11/16/12]
Subject: Cadence follows up with some details on those 14 nm IBM tapeouts
> The engineers at IBM had just taped out a chip in IBM FinFET 14 nm with
> an ARM Cortex-M0 processor, some SRAMs, and a mess of ARM/Artisan logic,
> using Cadence Encounter Digital and Virtuoso. ...
>
> Anyway the IBM research guys spun off 3 different routing styles to see
> how it would impact power, yield, timing, costs, etc.
>
> - from http://www.deepchip.com/items/0513-08.html
From: [ Wei Tan of Cadence ]
Hi, John,
The 4 tapeouts were a way for us to determine the effect of uni-directional
vs. bi-directional routing -- and with/without via bars. (Of course, the
majority of designers would want the ability to do bi-directional routing
with via-bars at 14 nm, which is why the process and NanoRoute needs to be
able to support that.)
We already have support for uni-directional and bi-directional routing in
Encounter Digital since release 9.1, and via-bars since release 10 -- but
the 14 nm-specific routing tests were performed specifically in Encounter
Digital 11 USR2 using these features.
For double patterning, in general it imposed only a very slight increase in
wire length compared to no double patterning -- mostly within a couple of
percentage points. Using double patterning increased via count by about
5-10% over no double patterning. Using uni-directional routing saved a
little (about 10%) on the wire length increase, but added another 10% to the
via count increase, when compared to bi-directional routing.
Of course, not using double patterning is moot for 14 nm, since at the 64 nm
metal pitch used for 14 nm, double patterning is definitely required. The
key is how EDA tools will allow for double-patterning-correct P&R while
minimizing the wire length impact.
---- ---- ---- ---- ---- ---- ----
> Then Encounter Digital was used to layout the entire design using all
> sorts whizbang FinFET 14 nm special stuff like double patterning, etc.
> plus built-in Cadence QRC Extraction.
>
> - from http://www.deepchip.com/items/0513-08.html
The 14 nm FinFET process extraction was a lot more involved compared to
extracting planar transistors. Tcap modelling was complicated because the
FinFET gate and fins and external contacts models are 3D. FinFET-gate-to-
source/drain capacitances are more complex than regular FETs. And from a
manufacturing standpoint, it's an entirely new process -- i.e. process
stacks, 3D effects, etc.
Also, there are resistance modeling problems as well since the current
distributions are non-uniform and require advanced modeling techniques for
accurate resistance.
Part of the reason why Cadence QRC (PVE 11.1.1) and Cadence ETS (v11.1) were
included as key pieces of the IBM 14 nm flow was to make sure they could run
extraction and timing analysis correctly on 14 nm designs.
---- ---- ---- ---- ---- ---- ----
> Anyway, this hybrid approach pretty much means "14 nm" will be faster,
> less leakage, less power; but overall area will NOT go down as one goes
> from 20 nm to "14 nm".
>
> - from http://www.deepchip.com/items/0513-08.html
I wouldn't discount the possibility of area savings with 14 nm from 20 nm.
Cell design will benefit from 14 nm design rules, and with that, std cell
placement and interconnect area can definitely be reduced.
Although the DRC and double-patterning (DPT) aspect is similar between 20 nm
and 14 nm, we know there will be lots of users who'll migrate directly from
28 nm to 14 nm as well. These new 28-nm-to-14-nm users will need to learn
how differently a DPT flow works.
Also, with wires getting longer and thinner, variability issues will become
critical to meeting timing while staying within the power budget.
---- ---- ---- ---- ---- ---- ----
> Although its called "14 nm", the IBM process is like the GlobalFoundries
> process where the FinFETs are 14 nm but the metal pitch is still "20 nm".
> (And because of Common Platform don't be surprised if Samsung's "14 nm"
> works the exact same way, too.)
>
> - from http://www.deepchip.com/items/0513-08.html
Since Encounter Digital release 11 already reads in 20 nm double patterning
rules, our P&R for 14 nm already automatically breaks the odd-cycle loops in
the metal layers -- so they can be decomposed into two different masks.
However, 14 nm design rules are still different from 20 nm design rules due
to shrinking geometries and the FinFET structure of std cell devices, so our
EDI System still has to parse those new 14nm rules and route them correctly.
That's why I'd say from a user perspective Cadence Digital P&R at 14 nm will
be somewhat similar, but our tool would have to do more work.
---- ---- ---- ---- ---- ---- ----
In closing, I'd like to point out to chip designers that using IBM 14 nm to
design will:
1.) give you a faster chip at the same power,
OR
2.) give you a lower power chip at the same speed,
OR
3.) a small bit of both.
In general, moving to 14 nm lets a design use less power OR run faster; it's
not something where every metric dramatically improves simultanously.
---- ---- ---- ---- ---- ---- ----
My other closing is we're still at a relatively early stage with the 14 nm
library and 14 nm process development. This means library developers and
process technology developers can get feedback from each other to influence
both of these ingredients -- as opposed to a later one-way street where
library developers just build with what they get from the process.
As a result, IBM, ARM and Cadence's joint involvement in these tapeouts at
such an early stage is definitely a great start, in my opinion.
- Wei Tan
Cadence Design Systems San Jose, CA
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