( ESNUG 498 Item 6 ) -------------------------------------------- [02/07/12]
Subject: (ESNUG 497 #6) Shawn "corrected" on how Spyglass Power really works
> Regardless, if there's only one take away that I want your readers to have
> here is that Calypto does RTL power optimization, too! PowerPro looks
> across 100's of cycles, while Atrenta Spyglass Power & Apache PowerArtist
> are limited to only a few clock-cycles.
>
> - Shawn McCloud
> Calypto Design Systems Santa Clara, CA
From: Narayana Koduri <narayana=user domain=atrenta not calm>
Hi, John,
I'm the Sr. Staff CAE responsible for SpyGlass Power at Atrenta and I wonder
how a marketing guy like Shawn McCloud, who was involved in high level
synthesis and Catapult C can make a comment on SpyGlass Power's ability to
"only look at power optimization opportunities across A FEW clock cycles."
Shawn is wrong.
The fact is SpyGlass Power's built-in formal/sequential analysis engines
look across SEVERAL HUNDRED cycles to find power reduction opportunities.
Other things Shawn may not know:
- SpyGlass Power uses our CDC engine to ensure that all the
power reduction opportunities it finds are CDC safe.
- Spyglass Power uses switching activity to measure power
reduction and it supports VCD/FSDB/SAIF formats.
- Spyglass Power also uses formal engines to do timing
exceptions verification.
- Spyglass Power supports UPF/CPF to do early RTL stage power
reduction all the way to post-layout.
- We have several other exploration tools to analyze design
activity, clock gating activity and memory activity that helps
the designer BEYOND what automatic power reduction can do.
Shawn may not know this, but our customers commonly get greater than 40%
power reduction using Spyglass Power.
- Narayana Koduri
Atrenta, Inc. San Jose, CA
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