( ESNUG 491 Item 9 ) -------------------------------------------- [05/12/11]
From: Dean Drako <drako=user domain=icmanage not mom>
Subject: A survey of 465 engineers on IP reuse and SoC-IC bottlenecks
Hi, John,
We ran our annual blind worldwide survey for the third year in a row. This
year a total of 465 engineers responded.
Our 2011 survey uncovered new information, including managing IP reuse:
1. Two Biggest Bottlenecks to SoC/IC design
2. Top challenges for managing semiconductor IP
3. Average time spent on Design Management tasks, including IP reuse
and bug management
TWO BIGGEST BOTTLENECKS TO SOC/IC DESIGN
"What two areas of the SoC/IC design process need the most
advancement over the next 2 years?"
EDA verification tools : ############################### 63%
IP collaboration tools : ######################### 50%
(selection-integration-reuse)
EDA design tools : ##################### 42%
Embedded software tools : ############# 26%
Other : # 2%
IP collaboration tools ranked higher in importance than EDA design tools!
A full 50% of respondents ranked it as one of the top two technology areas
needing focus.
TOP CHALLENGES FOR MANAGING SEMICONDUCTOR IP
"What are your top 3 challenges for managing semiconductor IP?"
Verifying IP : ############################### 62%
Integrating IP in design : ########################### 53%
Making internal IP reusable : ######################### 50%
Managing IP updates/bug fixes : ######################## 48%
Finding/Selecting optimal IP : #################### 39%
Tracking IP usage : ########## 21%
Other : # 2%
GSA had an interesting statistic highlighted in ESNUG 488 #2 - it said
that 66% of IP is developed internally, which underscores why designers
rated "Making internal IP reusable" and "Managing IP updates/bug fixes" so
high. And as always seems to be the case in semiconductor design,
verification challenges got the #1 spot.
AVERAGE TIME SPENT ON DESIGN MANAGEMENT TASKS
"What % of design or verification time do you spend doing Design
Management? Design Management time includes: Tracing bugs,
Finding working configs, Version control, IP collaboration..."
0% : # 1%
<10% : ################ 16%
10-20% : ###################### 22%
20-30% : ###################### 22%
30-40% : ############# 13%
40-50% : ######### 9%
50-60% : ###### 6%
>60% : ### 3%
Do not know : ##### 5%
The average time spent on design management (DM) tasks was 24% - this adds
up to over 1 day each week. The issues of bug management and integrating
both internal and 3rd party IP into the design flow have compounded the
traditional DM tasks of finding working configurations and revision control.
They now affect every design and verification engineer, for a significant
portion of every day.
A good DM system will let you import or link IP from multiple design
management systems for faster integration into your existing design flow,
and more quickly trace bugs and propagate fixes.
- Dean Drako
IC Manage Los Gatos, CA
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