( ESNUG 471 Item 7 ) -------------------------------------------- [02/19/08]
Subject: Brett Cline - The SystemC Poster Boy
Brett:
What important business appointment or task did you have to give
up in order to participate in this panel?
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When will SystemC grow up -- or will it stay a teenager for ever?
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I hear marketing types like Brett claim more productivity for creating
RTL. That's not a problem for good designers. What about real design
problems like timing closure and verification?
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Brett:
The world is dying to see what a DMA controller looks like in SystemC.
It's been over 12 months since the Bluespec challenge -- and a DMA
controller can't be more than a couple days work. Does it just take
too much time to build one in SystemC? Or, are you concerned that it
won't look much better than RTL? Which is it?
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For Brett:
Which language is winning these days for ESL, SystemC or AnsiC?
So, was last year the year of SystemC?
What happened to BlueSpec?
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For Brett: Is anyone really using high-level synthesis from SystemC?
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For Brett:
Every time I try to hire a System C Engineer, the guys in personnel
send me a bunch of people who have lots of experience putting GUIs
on Real Estate Data Bases. Can you give me one good reason why I
shouldn't just convert the whole thing to System Verilog?
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To Brett Cline:
AVM supports both System Verilog and SystemC. What about OVM? Are
the SystemC guys going to join the OVM party, too?
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I think you should ask one of them "Who dresses you?"
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Do you miss the chicken suit?
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For Brett: TLM and SystemC seems to have captured in the past more
traction in EMEA and Japan but not really in US, why? Do you think
that TLM2 will be the vehicle for broader adoption of simulation
and virtual target by software developers (vs. real hw)?
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Question for Brett Cline:
All the recent activity in ESL is concentrated on Virtual Prototypes
for design and verification. ESL synthesis has saturated a very
narrow niche. Why should anyone care about ESL synthesis?
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For Brett Cline:
Judging by the comments on the SystemC TLM2 Draft 2 forum it looks
like the TLM WG hit another foul ball. It seems that in order to
accomplish their task they restricted much of their focus to memory
mapped bus architectures. This self imposed requirement makes
the TLM Draft 2 less generic than users like myself were hoping.
I'll be putting it on the shelf with TLM 1.0.
Will there be a TLM2 Draft 3?
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