( ESNUG 471 Item 4 ) -------------------------------------------- [02/19/08]
Subject: Dennis Brophy - Accellera vice chair, Mentor standards guy
IS Mentor trying to accellerate standards, or are they creating road
blocks by sabotaging a verification standard via OVM?
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AVM was thin (at best).
OVM is pretty much 100% Cadence.
What does Mentor bring to the party?
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Ask Cadence/Mentor "When is Incisive/Questa going to support VMM?"
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I tried to interview a few key members of the VHDL group since
I had more than an intuition there was no real work done on VHDL
anymore. I got no such confirmation indeed (mostly a silence),
but certainly nothing denying this either!
So the not politically correct question to Dennis Brophy would be:
"When will the industry pronounce VHDL officially dead?"
To date, our mainstream designing language is still VHDL due to
our geographical situation (in Europe) but I can't wait until
customers switch to System Verilog.
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Dennis: How many end-users have taped out chips using UPF 1.0
specifically, not precursors to it. How many foundrys have
adopted UPF in their refernce flows. When will UPF ever be
available?
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How much business has Mentor generated since it aquired Sierra?
Exactly who have you stolen this business from? Name the specific
EDA companies? How long will it take for the Sierra acquisition
to pay for itself (if ever.)
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Why did Mentor buy Sierra?
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Dennis: Mentor has tried a number of times to enter the physical
implementation market and failed miserably every time. Why do you
think Mentor will succeed this time with Sierra?
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Question for Dennis: Did Mentor buy Sierra because you're tired
of being #3 or because you're afraid of dropping to #4?
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To Dennis:
With the release of the release of the open source OVM, will
Mentor and Cadence be donating this to Accellera as the standard
verification methodology? Both VHDL and (System)Verilog are
standards, why not have a standard verification methodology?
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Dennis Brophy -
Why did Mentor replace Mach TA with AdIT? I don't see any
technical reason for replacing Mach TA.
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Ask Dennis if OVM is just helping Mentor Cannibalize the Cadence
Verification customer base, or if it's actually creating inroads
with Synopsys shops?
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I am currently working on a project where I am modeling a design
using TLM2.0 draft 2. My question for the panel is the following:
Will the generic_payload class within TLM2.0 Draft 2 provide the
interopobility that the TLM committee claims it will, or will all the
extensions needed to use the generic_payload ruin that interopobility?
My feeling is that if you need to add extensions to generic_payload
so that it closer resembles the data class you want to send, then you
are violating interopobility and you might as well just use your own
data class.
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To Dennis Brophy,
When is System Verilog going to quit trying to perpetuate the illusion
that it's a singular, unified one-size-fits-all language? You can't
even use quite a number of the language's constructs among different
parts of the language, it's time to admit you have some work to do.
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For Dennis Brophy: Accellera has not had any activity with SystemC.
Why not? Should Accellera and OSCI merge?
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