( ESNUG 471 Item 3 ) -------------------------------------------- [02/19/08]
Subject: (empty chair) - Cadence Design Systems
Are Cadence's financial results as empty as this chair??
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To CDNS: Is CDNS planning to go private?
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How many former Enron accountants currently work at Cadence?
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For Cadence:
With your disastrous Q4 results and 2008 forecast will you move away
from "all you can eat" deals and start selling based on "value"
rather than financial incentives. Cadence ... please speak up I can't
hear you ... oh, you say you don't sell "all you can eat deals"???
Hands up in the audience if you've received tools "thrown in" you didn't
ask for/want as part of a "sweet" deal from your EDA supplier?
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For Cadence's chair:
Are you still selling software in India for 10% of the US list price?
Don't you think that this is contributing to outsourcing and the loss
of US jobs? What are you going to say when you get hauled before
Congress to discuss this issue?
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Cadence:
Why have you had so many lay offs recently?
Your stock has gone nowhere in 12 years, please explain why owning your
company by investors is not considered just dead money.
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Cadence's empty chair: How does it feel to be #2 (again)? Are you
going to try harder? Mike Fister's recent conference call reminds me
of the conference call that led to Jack Harding's departure from
Cadence. Deja vu?
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For Cadence:
I hear you are fielding an ESL synthesis product? Aren't you a
little late to the game? (by several years!)
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Non-Existent Cadence Person: How many end-users have taped out
chips using CPF 1.0 specifically, not precursors to it. How many
foundrys have adopted CPF in their refernce flows. How long has
CPF been available?
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Cadence
Ask Cadence how many tape-outs they have with ETS-XL.
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How long can the e-language last as a verification language?
I think that the e-languag should give place to the new emerging
System Verilog sooner or later. Somebody say that the e-language
may last 5 years at least because of verification IPs written in e.
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Cadence: - How many companies use Cadence PVS (Assura Physical
verification follower) productively ?
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Cadence,
Do you ever regret letting Joe Costello go? Do you hope you could
get him back, thinking he could do for Cadence what Steve Jobs has
done for Apple?
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Ask Ted: "Why has Cadence stock tanked so horribly?" It's $10 now.
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Formal verification seems to be increasingly more difficult due to
optimizations performed during synthesis. The Formal tool does not
understand the changes made by the synthesis tool. I know that
Synopsys claims that they have a solution via the file that they
dump during synthesis which can only be read by Synopsys Formality.
It seems that most people don't accept this. What is Synopsys and
Cadence doing to help with this?
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To Cadence, my edgy question would be :
Why is NC-Sim (Incisive, etc) lagging behind the other players
for System Verilog support?
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Ask Cadence/Mentor "When is Incisive/Questa going to support VMM?"
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Q. for synopsys/cadence
Why dont they just fix the bugs in the current versions of their
software then leave it alone and not go adding in heaps of 'new
features' which dont work properly?
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To Cadence: When are you going to fall into line and support UPF?
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Ask the Cadence guy:
You had a big part in the place&route industry 10 years ago. Are
you planning to re-gain it back? Will you have a leapfrog product
for future advanced processes of 45 nm and beyond?
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Since it's troublemakers... Make sure you stuff a Cadence t-shirt
to put in the empty chair. ;^)
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for Cadence
- will you allow other vendors tools access to Pcell layout cached
with Express Pcells?
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To both:
Development of support SVTB seems to have stopped, just short of
making SVTB useable. Why is that? When will the job be done so
SVTB can really be used?
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For Cadence:
When are they going to put their money behind System Verilog and
catch up to Synopsys in the verification arena?
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Increasingly we need to target lower power. It seems that the synthesis
tool don't address architectures that are more geared towards achieving
lower power. What is Synopsys, Magma and Candence doing to allow power
reduction of at least 20% to 25%?
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Question for Cadence
What is Cadence planning to do in the area of physical verification: DRC
/ LVS? Is there anything new or do we have to rely on Assura or should
we forget about Assura and go with Mentor's Calibre once and for all?
Heard some major foundry discontinued Assura support for deep sub-micron
technologies. Any comment?
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How many users do you have today in OA? Do you have any idea why OA is
not as bucketful as originally envisioned? Which version is stable for
the users to start looking at, without spitting blood?
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What is the status of 6.1 and how many companies adopted it?
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When do we get the promised full custom router that will compete with
Pulsic's Lyric router?
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Is PVS a myth or a real tool? Any details about the real release of
this "powerful, hierarchical, unlimited, multithread, etc."
verification environment?
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