( ESNUG 471 Item 2 ) -------------------------------------------- [02/19/08]
Subject: Paul Lo - SVP&GM of Synopsys Analog, former Avanti president
How painful was the Synopsys-Avanti merger? Are all the crazy wild
rumors about Gerry Hsu true?
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For Paul:
How much money did Synopsys give to politicians last year? Do you
think you got your money's worth?
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Ask Paul Lo why SNPS paid spot bonuses to employees the same week
CDNS shares imploded.
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Formal verification seems to be increasingly more difficult due to
optimizations performed during synthesis. The Formal tool does not
understand the changes made by the synthesis tool. I know that
Synopsys claims that they have a solution via the file that they
dump during synthesis which can only be read by Synopsys Formality.
It seems that most people don't accept this. What is Synopsys and
Cadence doing to help with this?
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Ask Rajeev and Paul to describe the analog design market landscape
5 years from now.
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I have used Design Compiler since 1992. In that time, I have yet to
use any release that did not core dump, produce bad logic, introduce
timing loops, or otherwise have serious problems.
When will Synopsys ever take software quality seriously?
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Wondering if Synopsys will start to bring down the DC Ultra features
to DC prices, so old DC customers can continue to afford the features
that are required for 65 nm engagements...
We either HAVE to buy Ultra to get the Topo features for 65 nm, or
start delivering RTL to our ASIC vendors, in which case Synopsys has
priced themselves out of a whole class of customer. We think they
need to start thinking of the physically aware tools as becoming
baseline, and start pricing them that way (or at least get closer).
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Question for Paul Lo:
The US perpetual list price for Synopsys CosmoLE Layout Editor is by
far the highest in the world (Quote = USD $127K each). What makes it
so special?
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Some questions for Paul Lo
- When are you going to announce your new OA based analog/custom
design tool Orion?
- What is strategy for winning against Cadence's huge install base
with the Virtuoso platform?
- Do you have any automation or other killer features that will
provide a compelling reason for people to look at Orion?
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When will the COSMOS replacement come out to market? What is the
name of the new tool and where can the progress be seen? Synopys
users want a challenge to CADENCE Virtuoso 6.1 environment!
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How will Synopsys move forward in the Analog EDA market, after the
reduction of effort for their Cosmos Suite? Will their new product
be integrated in the complete Milkyway database structure?
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Q. for synopsys/cadence
Why dont they just fix the bugs in the current versions of their
software then leave it alone and not go adding in heaps of 'new
features' which dont work properly?
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Question to Synopsys, analog block is also painful for digital guy in
terms of functional verification as well as timing model generation.
What is Synopsys view on current macro modeling on analog approach?
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To the Synopsys guy:
SNPS was talking a blue streak about UPF and then clammed up about
it after the acquisition of ArchPro - what's going on? Are SNPS
customers expected to use UPF or is SNPS going to push a semi-
proprietary low power design/verification/implementation flow?
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To both:
Development of support SVTB seems to have stopped, just short of
making SVTB useable. Why is that? When will the job be done so
SVTB can really be used?
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To Paul Lo:
When will Synopsys provide the source code of VMM to Mentor and
Cadence to enable them to support VMM in their simulators?
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To Paul Lo: When will Synposys join the OVM party? Rumour has it
that some customers already have VCS builds that support AVM2.*
and AVM3.*. Why is it taking Synopsys so long to more fully
support P1800 and hence OVM?
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To Paul Lo: Now that OVM is open source, when can we see VMM
being released under and Apache 2.0 licence?
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So Synopsys started the whole open concept behind System Verilog
and now Cadence and Mentor have decided to work together on OVM
(in theory open) but Synopsys is apparently sticking with VMM
which isn't open). Why not move everyone to the same open
approach based on full IEEE support?
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Ask Synopsys "When is VCS going to support OVM?"
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Paul Lo -
Why do you insist on selling two Fast SPICE simulators, NanoSim
and HSIM? Wouldn't it make sense to just merge the two?
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Increasingly we need to target lower power. It seems that the synthesis
tool don't address architectures that are more geared towards achieving
lower power. What is Synopsys, Magma and Candence doing to allow power
reduction of at least 20% to 25%?
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Questions for Paul Lo:
What % of Synopsys sales come from analog? Who are the major customers
that are using a complete Synopsys analog flow through to tape out?
Are there any plans to address RF or microwave design with the Synopsys
Analog tools? When, if ever, will they have a completely viable
alternative to the Cadence ADE?
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Paul, Synopsys has been making a major push in Silicon IP over the past
few years. Warren Savage has left to start IPExtreme, you have
partners/clients building IP in the form of pure play IP providers and
very large service companies in India (Example - Wipro). And you have
historically exited business like Emulation (Arkos) that are not core
to your software EDA business.
This business while growing does not seem a fit. Given the heavy
investment needed to stay ahead of the IP curve, what is Art's plan to
keep the investment going?
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