( ESNUG 462 Item 7 ) -------------------------------------------- [02/15/07]
Subject: Questions for Brett Cline, the SystemC Poster Boy
Brett Cline: For the last few years you tell us that next year will be
the year of SystemC. So, will next year be the year of SystemC?
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Is there any future for SystemC? Apart from Forte who seems to be selling
the concept of using SystemC as behavioral synthesis entry, the SystemC
community doesn't seem to be expanding.
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Is Forte in trouble? Why did they lose their second CEO in less than a
year? He joined in January, left in December.
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Why did you new CEO leave so soon? What does he know that we don't know?
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FORTE
I see more than 20 customers a month, a lot of them startups pursuing
very aggressive design targets - why no ESL there? Nobody is using it.
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Can Forte make money by any means other than selling off parts of the
company? (referring to the sale of the Chronology division to EMA)
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Is it true you are losing market share in Japan to Mentor Catapult C?
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Why did Forte fail in the Bluespec design challenge?
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Why did you duck the Bluespec design challenge?
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Bluespec is giving you a good run for the money. How do you plan to deal
with them?
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How many customers have you lost to Bluespec lately?
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Hey Brett, why not take the Bluespec design challenge? Chicken?
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Does Celoxica's recent "re-focusing" on "accelerated computing" and away
from ESL synthesis mean that the current crop of ESL synthesis tools are
dead? Or is the field too crowded? What makes Forte think it will be
a survivor, now that Celoxica has voted itself off the island? Who else
is about to be voted off?
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What's holding back ESL adoption? When are we going to have customers
take over the Poster Boy job? Where is the adoption?
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First you have to deal with System Verilog. Now you have an ANSI-C and
SystemC for ESL debate going on? In addition, Bluespec is sniping at
you. How are you dealing with getting hit from 3 sides?
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Brett: "It takes 6-7 months of C++ training and pilot projects to get
someone proficient (not an expert) in C++. Why take a great Verilog
engineer to make him a mediocre C++ programmer?"
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