( ESNUG 462 Item 4 ) -------------------------------------------- [02/15/07]
Subject: Questions for Ted Vucurevich, CTO of Cadence
Ask Ted Vucurevich if he thinks that Cadence having a seat on the Freescale
board of directors had any bearing on the Freescale switch to the Cadence
RTL synthesis tools? Most of the people I know or talk to, don't know of
a real technical reason.
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Open Access was born out of the Genesis project as a kneejerk reaction
to Synopsys proposing to open up MilkyWay, but has subsequently become
adopted by a lot of small and large companies. Is Cadence regretting
opening up their database to competitors, or is it going to go the whole
hog and open up SKILL and Pcells without which Open Access is useless in
the custom and analog design space (unless you use Cadence)?
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Is Cadence worried that the open Pcells and other scripting languages on
Open Access are going to allow their competitors to cut them out of the
market?
Has Cadence retrenched on the openness of Open Access?
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Is Cadence planning to end-of-life the Connections Program which allows
competitors access to its technology to develop interfaces to their
products, and use the sham of openness in Open Access as an excuse for
doing this?
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Ted Vucurevich: When he anticipates Cadence joining the Tcl era.
I'm just amused to hear the guy in my next cubicle learning Skill from
scratch every time he has to write a script for Cadence tools. :-)
I have nothing against Skill, but it has become the French of the DA world.
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To: Ted Vucurevich - CTO of Cadence :
1. Is "e" going to:
* win new market shares
* barely survive for a while
* get milked until a programmed death
2. When is Cadence going to support System Verilog fully and openly? As
far as I know, NC-Sim is lagging behind language support as compared
with Mentor/Synopsys.
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Cadence has to support both Specman/e and System Verilog for verification.
The quality of your current SV implementations is low and key features, like
constraints, clocking blocks, arrays are buggy. Why should we invest in
Cadence System Verilog when the other providers have definitely chosen the
System Verilog as their main route?
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Question about Specman vs. System Verilog for Ted:
How many _new_ Specman customers have you gained in the last year? I don't
want to hear about how many new licences you've given out, just how many new
adopters of Specman there have been.
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Which major Cadence customers are using the Framework 6.1 productively?
How many TO are already done with 6.1? How many P0 bugs - for 6.1 - are
"open" at the moment? Is it possible to switch to 6.1 without major
Cadence support?
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Question to Ted Vucurevich - CTO of Cadence
What is the real status of the Open Access and 6.1 migration within your
clients? How many clients already did it (number of seats)? Did they
dropped the older version for good, or do they keep it just in case?
What about migration of old databases to OA?
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When is OA and 6.1 ready for production? Are there any happy early adopters
ready to talk? What is the feedback in terms of cost to migrate and what
are in general the "bitter" corners of this exercise? If the environment
is ready as advertised why is the majority of the market is reluctant to
move into it? Bad memories from OPUS migration? Support of other vendors
to OA?
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It's an open secret that importing Verilog into DF2 is pretty broken. Can
we expect major improvements in 2007? (targeted to Ted Vucurevich)
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I've been using System Verilog on an ASIC design for 13 months. Mentor
and Synopsys have SV support and methodology in place and growing. Why has
Cadence been completely silent on the issue, and don't give me that "SV is
not mature or adopted yet." It's here, and it works. You're late!
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To Cadence and Synopsys.
We use a Cadence NC-Sim/Specman combo with Synopsys Design Compiler for
synthesis. What we forgot was their System Verilog interoperability;
they do not support the same subset of the standard!
When will it be possible to run verification on code that's synthesizable
and vice versa in System Verilog with industry standard tools? (I don't
doubt that it may be possible with a pure Cadence or pure Synopsys
solution -- but for various reason's that is not desireable...)
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Question for: Ted Vucurevich - CTO of Cadence
We know Cadence is talking of both "e" and "System Verilog". And their
competition is strongly pushing System Verilog. So what is Cadence's long
term game plan and take on this? Will they be equally pushing both of
these or what?? And what happened to "SystemC"? Somehow in the "e" vs
"System Verilog" battle, we have stopped hearing about "SystemC" even
from Cadence?
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This is a question to bat around between Ted and Antun:
Verification of power domains, power isolation, level shifter insertion,
etc. is a real concern during design. Why have Cadence and Synopsys
decided to be totally incompatible with each other?
One inlines everything, the other adds extra files to the side. Imagine
our scenario where the tool set is: NC-sim simulation, DC synthesis,
Conformal LEC for FV. I have to maintain, and make sure they match, two
complete sets of power directives. Why?
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This question needs to go to both Cadence and Synopsys.
Why must the industry waste so much resource on defining "proprietary
standards"? The big EDA companies, i.e., CDN and SNPS, are wasting their
resources and holding back the industry with silly battles over ECSM vs.
CCS and CPF vs. UPF. No wonder growth prospects aren't enough to excite
Wall Street -- we keep reinventing building blocks rather than
innovating.
What concrete steps would these leaders propose to adopt true industry
standards in these areas? And no, just saying "the other guy must give
in and adopt our wonderful standard" is not an answer!
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For Ted... What is the deal with CPF? It just makes us lose respect for
Cadence. At best, you are creating yet another CCS/ECSM battle.
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Concerning the library format extensions to Liberty, could it be possible
to make agreements on one standard instead of two? It's VERY annoying to
be forced to support 2 formats. (ECSM from Cadence and CCS from Synopsys)
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Ted Vucurevich (Cadence) - The low power initiative continues to be a
political battle between the big EDA companies. Is Cadence really interested
in unifying the low power standards with Acellera's effort on UPF or is it
just a lip service, while you continue to strong arm CPF as the standard?
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The new Cadence licensing for its analog tools is really just a price
raise. Why didn't Cadence just announce its raising its prices?
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Your new organization Manufacturing Model Interface offers a great vision.
BUT, beside CMP area, when can you show the "beef?"
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For Ted: Cadence's CEO has publicly proclaimed the company will "grow their
own" technology as opposed to the reckless acquisitions of the past 7 years.
Yet, there does not appear to be any areas where Cadence has delivered truly
innovative technology to the market since this proclamation. Can you cite
anything Cadence is doing differently in terms of strategic planning or
software development that would give us confidence that eventually something
new and exciting will come out of the Cadence "grow your own" tact?
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Cadence
Most of your customer support appears to have moved offshore (to Noida and
Bangalore, India). Is this a good thing for your customers?
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TedV: We understand that your "kits" aren't really selling; they're simply
a marketing strategy and what you really sell are FAM deals for products.
They use the kits to get press but what they are actually selling is the
same old same old... if you got a sales report, the unit sales
of Wireless Kit would be very low. Are these rumors true?
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Ted Vucurevich - CTO of Cadence
The current generation of ASICs requires design teams of 40-50 people.
Given the management problems associated with the current RTL design
methods, my question is: Are Verilog and VHDL obsolete?
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What is the status of PVS? Ready to compete with Quartz? If yes, can we
get some details from the early adopters? Who are they?
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Question for Ted Vucurevich.
Two CDNLives ago the Keynote featured your new, hot tool, PVS. This was
going to be the tool to supplant Calibre by being faster, as accurate
and require no further library resources by reading the Calibre rule
decks. Since then we have not heard anything about it. What is the
status? Are there any production users (not just evaluating). How does
it compare to Calibre now that it has hyper, turbo and mtflex available?
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Ted - Why have not heard of a single success story of Cadence PVS getting
any market share from existing tools?
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IC Craftsman is out of steam, when do you plan to bring a new router to
the Analog users? Will the new router address electromigration, IR drop,
analog constraints? Are there any advanced users who work with Cadence
to build it? Who?
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The EDA vendors - including Cadence - have a reputation of pre-announcing
and creating slide-ware. How can the CTO control the marketing people to
make sure that the industry credibility is not hurt?
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Cadence
There's no common timing engine for your tools. Think of all of their
acquisitions like CeltIC is still not completely integrated with Encounter,
VoltageStorm either. There is a difference between integration (engr) and
bundling (mktg). For example, the timing engine in their optimization tool
is different from the timing engine in their analysis/signoff tool.
Is the product lineup just too unwieldy to change? Are you losing business
because of this?
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Cadence FMS is a good base, but what is the roadmap ? (ie.: multiple runs
on same block, user modifiable windows, better interface w/3rd party tools)
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What the f**k are you doing building a new 5-story, 208,000 sq ft building
when the main San Jose office is nearly empty? A lot of the employees are
now working from home and it's a ghost town in the office, cubes are always
empty. This is a flagrant waste of investor's money. How about they
provide badge data to show how many people enter the building on a regular
basis, consolidate and then have enough room for significant R&D growth?
I want my stock price up and bonuses paid, not a new building. Why is
Cadence building this new building?
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