( ESNUG 462 Item 2 ) -------------------------------------------- [02/15/07]
Subject: Questions for Antun Domic, GM of Implementation, Synopsys
Why does Synopsys bring out the lawyers when it's losing a technology
fight? Nassda, Magma, etc. Who are you going to sue next? Sierra?
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Q: Are you going to buy Magma or destroy Magma with the patent lawsuits?
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To Magma and Synopsys --- what do you think are the fallout of the legal
battle? If Magma loses the appeal, what are its backup plans? If Synopsys
loses, what are its backup plans?
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Recently a senior member of the Synopsys silicon group joined the Cadence
silicon group in a very senior position. How is Synopsys going to protect
its IP due to this move especially in its DFM activities?
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There are 20 or so DFM companies. How do you segment the market and how
many of them will you buy?
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Is simulation dead? With STA so complex and advanced these days, why should
anyone bother to buy any Verilog, VHDL, or System Verilog simlators? Are
your VCS sales dying because of your PrimeTime sales?
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What is Synopsys going to do to counter the Cadence ETS threat to the
PrimeTime monopoly for static timing signoff?
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Why are you starting to blackmail customers who just want to buy your IP but
don't want your antiquated tools? Is it because Cadence has an answer for
DC and PrimeTime now?
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Why is Synopsys making its software so kernel specific. They are now
migrating their RHEL in A-foundation to a different RHEL version. They
keep changing the kernels (which will not support older versions of
Synopsys tools) for the newer kernel versions and cause so much pain to
their customers to make these changes. Why do they do this? They are
software engineers and should make sure their code works across multiple
kernels.
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Antun Domic - Why do you still promote two Fast SPICE tools - HSIM and
NanoSim? Wouldn't it make sense to offer a single simulator?
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Antun Domic: Why, in this day and age, does Synopsys still dictates weird
ASCII formats that are not:
1. Tcl morphed (command arg1 arg2 ...)
Or
2. Released with official yacc code
I mean, DEF is old news but CCS could have opened a new page. Did anybody
try automating PrimeTime/PrimeTime-SI report reading?
Flow automation is done by customers individually according to their local
cultures and methodologies. Why not help us read and manipulate your
formats? That could be more helpful than RAM or GRF.
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This is a question to bat around between Ted and Antun:
Verification of power domains, power isolation, level shifter insertion,
etc. is a real concern during design. Why have Cadence and Synopsys
decided to be totally incompatible with each other?
One inlines everything, the other adds extra files to the side. Imagine
the scenario where our tool set is: NC-sim simulation, DC synthesis,
Conformal LEC for FV. I have to maintain, and make sure they match, two
complete sets of power directives. Why?
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This question needs to go to both Cadence and Synopsys.
Why must the industry waste so much resource on defining "proprietary
standards"? The big EDA companies, i.e., CDN and SNPS, are wasting their
resources and holding back the industry with silly battles over ECSM vs.
CCS and CPF vs. UPF. No wonder growth prospects aren't enough to excite
Wall Street -- we keep reinventing building blocks rather than
innovating.
What concrete steps would these leaders propose to adopt true industry
standards in these areas? And no, just saying "the other guy must give
in and adopt our wonderful standard" is not an answer!
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You guy support UPF. Great! BUT when can your tools in low power flow
be able to run following the UPF?
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For Synopsys/Magma
After CPF was passed to a neutral standards body, why was UPF pursued even
though CPF was largely complete and UPF was merely at the "idea" stage?
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Antun, do you either trust or distrust Steve Schulz and his Si2? Is
Open Access a Cadence standard or an open standard?
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Concerning the library format extensions to Liberty, could it be possible
to make agreements on one standard instead of two? It's VERY annoying to
be forced to support 2 formats. (ECSM from Cadence and CCS from Synopsys)
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For Synopsys -- Why do you think that you get a hall pass for not truly
opening up .lib and .sdc? Isn't that a double standard? (pun intended)
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For Antun:
Do you see any path where an efficient compile in DC, using all the
optimization power, can have formal verification applied, and not use
binary files passed from DC? If I'm trusting the FV tool to tell me my
gates match, I sure want to be able to *SEE* what it is making that
judgment from. "Under the hood" just doesn't cut it when mask sets cost
in millions.
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Is the ICC router more than just a wrapper around the Astro router? When
he says yes, ask what more specifically is in ICC.
Why should I pay double the price for IC Compiler?
How many Synopsys AEs understand both IC Compiler and Astro?
De Geus's Law: software prices double every few years.
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Please ask Antun just when Synopsys will stop its death spiral by getting
a new CEO and executive management team? The company's current situation
is similar to that of Mentor in the late '80s and early '90s, when Mentor
CEO Tom Brueggere clung to his CEO post while his company plunged into a
sea of red ink and lost its market leadership under attack from Cadence.
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When will Synopsys acquire Jasper so that Kathryn Kranen can be groomed to
take over for Aart?
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Antun:
Multi-CPU machines have been available for several years now, when will
there be a multi-CPU version of PrimeTime available to take advantage of the
other 3 processors on our machines (where you can take a single run and
distribute it across N CPUs to get a speedup of N... not just the "job
distribution" you currently have where you take 10 jobs and distribute
them across 10 machines.)
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Ask Antun Domic
Why we were told that Physical Compiler was the best tool ever when it
first came out. We then later found out that the synthesis engine in
PhysOpt only did a few of the dc_shell bag of tricks when they started
pushing DC-Topo. Is DC-Topo a backdoor price raise?
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Approximately what is the bug count on Design Compiler, and has it been
increasing or decreasing over the past 3 years? (targeted to Antun Domic).
Is it true that DC-Topographical uses the same placement algorithms as
Physical Compiler, it just doesn't let you save the placement results?
(targeted to Antun Domic).
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Are people really buying the idea of DC-Topo where if you run the same
placement tool 2X (once under the hood in DC Ultra and once in IC Compiler)
on the same netlist you get about the same answer as a solution to the
interconnect modeling problem?
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Is DC-Topo really doing an actual placement under the hood or is it some
kind of "virtual placement"? If it is a true legal placement, why can't
DC-Topo write out DEF?
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Why is the VMM code still not freely available? Is it because you want
your customers to use the AVM instead? Or is the implementation so lousy
that you are ashamed to show it?
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Question about VMM for Antun:
Is VMM actually written in Vera, not System Verilog? If not, why won't you
release the code? AVM is open source, and Cadence say their P2C libraries
will be. Why not yours?
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Antun Domic (Synopsys) - How do you expect to continue innovation when
majority of the R&D work force is moved offshore (ie. India) just for the
sake of saving cost?
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Please ask the Synopsys guy about the "openess" of Vera. They had promised
a long time ago to open the whole language, yet my impression is that they
have only opened the core of it.
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To Magma and Synopsys --- what do you think are the fallout of the legal
battle? If Magma loses the appeal, what are its backup plans? If Synopsys
loses, what are its backup plans?
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To Cadence and Synopsys.
We use a Cadence NC-Sim/Specman combo with Synopsys Design Compiler for
synthesis. What we forgot was their System Verilog interoperability;
they do not support the same subset of the standard!
When will it be possible to run verification on code that's synthesizable
and vice versa in System Verilog with industry standard tools? (I don't
doubt that it may be possible with a pure Cadence or pure Synopsys
solution -- but for various reason's that is not desireable...)
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Antun - What is Synopsys' position on SystemC? If you think System Verilog
is a better choice, why do you still sell Cocentric SystemC Studio? Are you
just trying to cover your bets?
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Antun, are you going to buy Synplicity to break into the FPGA market, or
are you just going to continue to try and become a DFM company, even though
the amount of research needed to even begin in that market is out of any
single company's league?
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Many of our large designs use FPGAs to demonstrate correct operation with
the intention of eventually porting to ASIC technology. Often, "eventually"
never happens. My question is: are we going to see integrated tools for
the FPGA-then-ASIC design cycle, or do I have to continue to use the crazy
mix of kludge tools we've got now?
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To Synopsys:
After all this time is anybody using System Verilog for design?
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Cosmos is dead, what/when is coming the answer from Synopsys to Virtuoso?
Is it true that most of this effort is concentrated in Armenia?
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Can Hercules do 65, 45 and 32 nm? Is Synopsys working on any new
development to answer Quartz (Magma) and PVS (Cadence)?
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When will Hercules be integrated into ICC and will the engine be utilizable
to allow DRC clean 45 nm routing?
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Is Synopsys ever going to release a real database? Or are they just going
to continue and attach files, stick a feather in their hat, and call it
macaroni?
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