( ESNUG 452 Item 4 ) --------------------------------------------- [02/17/06]
Subject: Questions for Ted Vucurevich, CTO of Cadence
Edgy question for Ted
Why did the business model of Cadence Design Foundry fail?
A follow up would be to ask what Synopsys did right with their Design
Services that Cadence did wrong?
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Ask Vucurevich if they sold Freescale managers "foilware products" to get
the deal signed? Had they figured the Freescale managers would never admit
that they had been taken even after evals showed there were gaping holes in
the flow.
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for Ted Vucurevich
Is Open Access a real Cadence attempt at openness in the industry, or
is there a risk it will be used as an excuse to remove inconvenient
competitors from the Connections Program? I.E. the excuse would be
"You can get at the database now so you don't need to have access to
Cadence's tools to deliver the services you want" -- which ignores
that the customer needs seamless integration not just data transfer.
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Ted Vucurevich - CTO of Cadence
I love the Open Access database. Is there a distribution and support
model that will actually work for it? Will any other EDA vendor use it?
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Questions for Ted Vucurevich:
What's going on with Open Access? What's the real adoption rate?
What's the point of developing a Specman "standard" that is only supported
by your company ("e")?
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Ted Vucurevich:
Cadence is still trying to sell a Verisity Specman "e" as if it's the
best thing out there. I don't see any Specman discussions or sessions
here on the DVCon agenda. You intend to fold System Verilog into your
suite. Neither of your competitors are looking at Specman. It looks
like "e" is going the way of the 8 track.
Why are you pushing "e" Specman? Do you have the people to support both
"e" and System Verilog solutions? If not, which one does Cadence intend
to drop and why?
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Ted Vucurevich - CTO of Cadence
how does he respond to the perception that Specman is terminally ill
according to other surveys at deepchip.com regarding verfication tools?
(prognoses: less than 5 years)
i know it might be a bit "vague"... but, i think asked in this manner
allows him to answer the question in a tell-tale way, whatever the
answer may be (?)
you might lead him into a question regarding System Verilog and how
Specman can "compete"... we all know they are going to "support System
Verilog in design space" (duh, it is just a stub), but in verification
space, how do they complement each other (to use a marketing word); how
does Specman plan to coexist, or possibly, "rise above" System Verilog?
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Why did Cadence acquire Verisity for $315 million in cash? In hindsight
was it worth the price?
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To Ted Vucurevich (Cadence):
What is the future of Specman? Since the acquisition, there is hardly any
mention of Specman or 'e' in the verification world.
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To: Ted Vucurevich - CTO of Cadence
Cadence seems conflicted with respect to the Verisity acquisition. You
support e, System Verilog and SystemC, yet not equally. You have two
emulation solutions, yet they are supposedly orthogonal. When will you
truly have a cohesive solution and finally integrate the company?
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I'd like to ask the following to Ted Vucurevich of Cadence:
Given the recent acquisition of Verisity (by Cadence) has effectively
eliminated the possibility of 'e' becoming a universal verification
language, when does Cadence plan to end-of-life the support for 'e' in
their EDA tools?
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Ted Vucurevich - When is Cadence resurrecting the Get2Chip architectural
compiler? Does that mean they are abandoning System Verilog for SystemC?
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Ted Vucurevich - CTO of Cadence
Rumor is that Cadence is bringing back Architectural Compiler from your
Get2Chip acquisition. What are Cadence's plans in the SystemC ESL market
and do you have a synthesis tool?
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I would love to know where emulation stands at Cadence. When will a chip
designer be able to emulate his design at a reasonable clock speed?
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Question to Cadence CTO: What's your take on what Gary Smith said in the
SNUG 05 #13? i.e. "For the bulk of 65 nm and below, the battle is between
Magma an Synopsys"? Where are the Cadence 65 nm routing tapeouts?
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To: Ted Vucurevich of Cadence
How many production IC 65 nm tapeouts have used Cadence backend flows and
how complex were these designs in terms of gate size, clocking, etc. ?
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4) Vucurevich:
The Catena group's recent announcement took great pains to say "It's not
a router". Surely they are working on one? How on earth will this fit
into the already overcrowded router Cadence arsenal?
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Ted Vucurevich - CTO of Cadence
Do you have any new routing technology for analog world? If yes, when
it will be ready for real production?
What is Catena and what is their next BIG priority?
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Ted Vucurevich - CTO of Cadence
I remembered that Astro route is based on GRID.
Magma said they route is based on SUB-GRID.
Cadence Nanoroute is based on GRAPH.
I'm comfuse about Nanoroute based on GRAPH.
What is route based GRAPH? Different from the others?
He is a technology officer. He should know this.
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Question for Ted V. on the latest announcement of Chip Optimizer:
Are we to believe that this new "break-through" technology is supposed
to replace classic OPC/RET tools? Does Chip Optimizer just make incoming
designs more "lithography friendly"?
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A couple of question For Cadence CTO
Q1 - Cadence has 4 different main tools for Physical Layout Verification
and analysis (DIVA, Dracula, Assura, PVS and probably other for specific
application and flows (i.e. Fire&Ice). What they are going to propose to
their customers to help to made the right choice? Buy the most expensive?
Q2 - Are there any Cadence R&D project to design Analog (block or IC)
taking under control all the re-emerging issue like latch-up, leakage and
all the typical physical-connected parasitic phenomena that now are more
and more visible in the latest technology node?
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Question for Ted Vucurevich - CTO of Cadence
Last year I heard that Cadence was going to launch a (yet another) physical
verification tool to fight Calibre. Supposedly this new tool would out
perform Calibre. What is the status of this? Was this just another Cadence
marketing anouncement?
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For Ted Vucurevich:
Are they planning to do away with the Encounter Test product?
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How new an idea is Mike Fister's concept about vertical applications
platforms? We had a run at that about 10-15 years ago. I mean, do
people remember the Alta Group, for DSPs?
How effective will these specialized vertical platforms be if the
horizontal design flow is mediocre, at best?
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Questions for Ted Vucurevich - CTO of Cadence
Why did Cadence shut down Telos Ventures? What happens to the companies in
which Telos had made an investments? Will Cadence continue financial support
of the companies in which Telos made the initial investment?
Telos portfolio companies include: Clear Shape, Coventor, Lorentz Solutions,
PDF Solutions, Ponte Solutions, Virtutech, Xpedion Design
Follow up to Atul Sharan - CEO of Clear Shape
Atul, does Ted's answer correspond to your experience of how Cadence will
honor the commitment made by Telos?
Is Jim Hogan still on Clear Shape's board of directors?
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I would like to direct my question to Ted V and Antun.
Why do you insist on customers running Linux distros that went out with
the dinosaurs? Does Cadence and Synopsys really understand the Linux
culture and development model? Why can't they be LSB compliant so they
can support and promulgate the latest technology? Why are they so hung
up with RedHat? There is more to life than one OS packaging company.
And don't feed us the standard bullshit of support matrixes and cost.
It's all the same freaking code in all the distros written by the same
core group of people. Why are they not taking a lead in LSB rather than
just playing lip service?
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For Ted Vucurevich:
Cadence has been milking Virtuoso and not putting the necessary
resources into its further development. In particular, the
connectivity model is known to be fragile and limited. It seems
that Cadence keeps remodeling the nest but not fixing the ills
of the goose!
What plans do you have to upgrade or replace Virtuoso?
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