( ESNUG 452 Item 2 ) --------------------------------------------- [02/17/06]
Subject: Questions for Antun Domic, GM of Implementation, Synopsys
To Anton
Why is IC Compiler so weak? Cooley bashes you for it not catching on
like Physical Compiler did with customers. What say you?
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Antun - Synopsys
IC Compiler is a major vertical bundle. What if customers do not want to
use the Synopsys xtalk, rail, floorplanner, etc.? IC Compiler-PhysOpt is
another big bundle product. Will regular non-bundled PhysOpt continue to
exist for people who do not want the kitchen sink with their placement
engine? What becomes of our beloved Astro in the era of IC Compiler?
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I have one for Synopsys:
The IC Compiler adoption seems to be much slower than the Apollo to Astro
migration. Do you agree/disagree? If agree, then why is this the case?
When do you feel that at least 50% of your P&R users will be using ICC?
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Ask Antum Domic why they lied to their PhysOpt users about PhysOpt when
they knew it was a "hog tied" version of DC's logic optimization engine
and why it took them so long to come clean.
Ask him why they couldn't make the full DC engine work in the physical
domain? Was it a run time issue?
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Antun Domic - GM of Implementation, Synopsys
What is happening to Cosmos? Is it still somewhere on your map or are you
just giving up to Virtuoso on this effort?
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Question to Antun Domic:
While SDC code is becoming as big as RTL code, many tools are available
for RTL, but not for SDC creation, debugging, equivalence checking etc.
While designing big SoC's, constraints are one of the most relevant
sources of issues, with direct impact on project schedule (everything has
to be "hand verified".)
Does Synopsys acknowledge the problem? If so, what are its plans?
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Antun Domic - GM of Implementation, Synopsys
1) Tapeout is often a rush between STA and LVS/DRC. With people like
Mojave speeding up LVS/DRC an order of magnitude, tapeout is now gated
by PrimeTime runs. When are you going to have true (n-way) multi-
processor support in PrimeTime?
2) Is DC in the situation that Calibre was in 2 years ago? (monopoly, tool
that is 5+ years old, tool that is evolutionary versus revolutionary,
your company willing to use the monopoly position with it prices, and
Mojave, Hercules, Cadence coming up?)
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For Antun Domic (Synopsys)
How can a new EDA company can grow in the market if there is no real inter-
operability with the well established tools developed by Synopsys on the
Milkyway platform?
Should a small EDA startup spend money and resources to support Cadence
Open Access and Synopsys Milkyway in the same time?
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Antun Domic - GM of Implementation, Synopsys.
What about open databases? Yes we tool users like them!
When are you guys going to do something internally and not just
sue and then buy companies and technology?
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Ask Antun -- "Which is bigger? By headcount, the Synopsys Legal Department
or his R&D group?"
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Do current Synopsys tools use any of the patents you're suing Magma over?
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Antun: Why do you think System Verilog provides an interesting increase in
the level of abstraction over standard Verilog? Isn't System Verilog just
a money grab by Synopsys to sell Superlog?
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Antun, Synopsys has acquired many companies. Recently Synopsys sold the
Encore technology & team to Sigrity. Which business is Synopsys is in?
"Buying and selling companies" or the "EDA software"? (John, remember
that Synopsys acquired VCS and then spun them out to become Viewlogic.)
Did Synopsys acquire Monterey for the purpose of owning the Monterey
Patents with and eye toward strengthening its lawsuit against Magma?
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Please ask Domic what is Synopsys' plans for a logic BIST testability
solution? LogicVision is going off the deep end. LV4.2b is filled with
bugs that they won't fix because they have thrown all of there eggs into
the LV2005 Bucket! They don't understand layout implementation. They
MUX clocks in ways that I didn't even think possible! Why doesn't
Synopsys just buy LogicVision, simplify its use by integrating it into
the tool suite and make all of us designers lives easier?
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Will System Verilog replace SystemC as a systems simulation language? Why?
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Antun Domic - GM of Implementation, Synopsys
At DesignCon someone from Synopsys tipped a SystemC-RTL equivalence checker.
When is that due out? Is Synopsys now supporting SystemC? Is a SystemC
synthesis tool in the works (again)?
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System Verilog Testbench is still a pipe dream. Based on what I hear from
their respective sales/AC groups, please consider the following questions:
Synopsys- I've spoken to the 4 different Synopsys AC/sales offices that
interact with various parts of our company and have gotten 4 completely
different answers to the following questions:
1) When will SVTB (System Verilog Testbench) be ready to go in VCS? I've
gotten responses ranging from "I've got customers using it successfully
right now!" to "It's broken. Definitely won't be ready for production
work in 6 months, or even 12 months. You could use it now, but you'd be
fighting tool bugs and installing patches on a weekly basis." We're
currently locked in to the proprietary VERA/NTB language, so that could
bias answers we've been getting.
2) How much more life does VERA/NTB have? We've got multi-year projects,
so putting all of our eggs in one basket that might not be supported in
the future is scary. We'd love to jump on SVTB as a permanent solution,
but I can't tell if you are truly having a difficult time stabilizing
SVTB or if you're intentionally dragging your feet to keep current
customers locked into your proprietary products. SVTB seems to be a
subset of Vera's functionality, so all you would need is a new parser!
If you concentrate on making SVTB the most accurate and fastest SVTB
implementation, you'll keep your current customers and probably add
some. If you concentrate your energies on keeping customers by locking
them in, you'll only piss them off and motivate them to spend the energy
to make a switch.
Cadence/Synopsys - Cadence Verification ACs have told me that because
SV's testbench features lack a "reference simulator" or even a clear-cut
specification with no room for interpretation, all EDA vendors will have
different implementations. This will not make SV testbenches any more
portable between vendors than existing 'e' or Vera testbenches. What's
the deal? In my little world verification is a problem that is hard
enough without EDA vendors making it worse.
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To Antun Domic (Synopsys):
Would Synopsys please focus on providing quality verification software?
In my two years as a VCS NTB user, I have yet to find a VCS release that
will work with other Synopsys products (like VMT, SWIFT and FLEX models).
I have now come to believe that indeed "you get what you pay for".
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I won't be there this year, but questions to ask Antun and Ted:
Your cash cows (Design Compiler, VCS, RTL Compiler, NC-Sim) have become
commoditized. While this is a good thing for customers, it's probably
not filling your pockets with gold.
Are Cadence and Synopsys two companies in decline? How do they plan to
counter this problem?
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When the EDA market shows anaemic growth, how do you plan to show better
growth for your company? Gobble up each other and raise ASPs?
Seems EDA is relatively flat as compared to the semi market.
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To Ted & Antun: (and even open it up for comments by others)
Linux and the OS kernel is a complex, complex thing. OpenSource
revolutionised the OS space. Do you think that open source EDA tools
are coming of age? Or, there is a potential for that? How will it
disrupt your business?
With Sun going opensource with their RTL (http://www.opensparc.net)
for their latest & greatest microprocessor, what happens to open
source IP? Could DesignWare go open source?
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I was reading a quote from a Synopsys guy the other day about outsourcing.
As I recall, he was going off about how India and China might be catching
up because they had more EE grads coming out of colleges there, which
were going to contribute to an ever increasing engineering pool.
I recall a few years ago that there was some controversy surrounding deep
discounting of EDA software to India, maybe even China, but it was
definitely a trend overseas. I'd like to know how can Synopsys keep the
US competitive, when they discount overseas EDA software, which basically
is a rebate for outsourcing?
I guess you could start with Synopsys, maybe ask Cadence and Mentor about
this, because I don't hear much about this lately.
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To: Antun Domic of Synopsys
Whats steps are being taken by Synopsys to ensure that we do not end up
with two independent timing modelling standards within the Liberty view
standard (i.e. CCS and ECSM)? Will the standards be merged and would
Synopsys support this venture?
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Synopsys: "When are you going to buy Forte Design Systems to re-join the
behavioural synthesis battle?"
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