( ESNUG 438 Item 17 ) ------------------------------------------- [01/18/05]
Subject: 11 Consultants on the Cadence-Buys-Verisity News
> Cadence announced it's buying Verisity for $285 million in cash.
>
> As an EDA user, do you think this is good news or bad news? Why?
As an EDA user it could be good news. Perhaps Cadence will beat
Verisity with a stick and improve their performance and garbage
collection issues. It would be interesting to see if they have a
combined Verilog/e kernel to counter Synopsys System Verilog.
- [ An EDA Consultant ]
Thoughts on Cadence-buys-Verisity:
1) I don't see quite what Cadence has bought. They get some very
smart R&D and field apps people, and some nifty testbench
automation technology, but $280M sounds an awful lot for that.
They also get the "verification process automation" stuff
(vManager), but... is the world really that interested??? And
they get a customer base. But those customers are, for the most
part, existing big EDA users who are very likely to be
Cadence customers anyhow.
2) The verification tool landscape is obviously affected. However,
it's not too clear to me how it will shake down. I can see 3
possible scenarios, and none of them sounds like a really good
deal for the industry:
- Cadence continues to support Specman and 'e' while
developing System Verilog testbench automation
features within NC-SIM. That dilutes their effort
and leaves us with the which-language-do-I-choose
problem that we all know and love.
- Cadence drops System Verilog like a hot potato,
and concentrates on Specman/e as its testbench
automation solution. That would make for Cadence's
SECOND about-face on System Verilog in only 2 years.
I'm not sure how the market (users, Wall St) would
perceive that, but it doesn't sound too smart to me
even though it might gain them some temporary
advantage over Synopsys.
- Cadence uses the Verisity technology and experience
to force the pace of its own System Verilog introduction,
and vigorously encourages existing Specman customers to
migrate to System Verilog. That sounds like a good way
to anger a big bunch of existing Cadence customers
who are also Specman users.
So, in summary, I don't see how Cadence push this forward without
pissing-off some big segment of their own market. I guess I'm
missing some part of the big picture!
- [ An EDA Consultant ]
Not so good.
- [ An EDA Consultant ]
I like seeing Verisity's risk takers rewarded, and I think that they
will benefit Cadence in a way that the sum is greater than its parts.
HOWEVER, I like standards. I believe that System Verilog is a well
designed language for design and verification. I hope and expect that
it will eventually prevail and become universal. I hope that Cadence
does not put its tremendous resources towards prolonging the peaceful
death of 'e', the Esperanto of verification languages.
- [ An EDA Consultant ]
Verisity has been shopping themselves for at least the last 6 months.
I think the sale was inevitable as Versity has some good core
technology and their stock price has been floating around the
bargain-basement range for a while.
From a user's perspective, this is very good news, particularly for
Specman users but also for future testbench tool users as well.
For the past 12-18 months, Verisity has been suffering from a serious
FUD ("fear, uncertainty, and doubt") problem in the market. Many
customers have been reluctant to renew their licenses, particularly
in the US and Europe, as they saw the SytemVerilog writing on the
wall -- when System Verilog 3.1a comes out, you will no longer have
to pay the big premium ($22K+/year) for testbench support. Synopsys
NTB had been making some good inroads into accounts by playing the
FUD card in sales. If Verisity had formed an early System Verilog
3.1a support story, they would have been able to offer their customers
a good co-sim or transition story -- and might not have needed to
sell out.
I think Cadence will run with this acquisition. The pricetag implies
that they didn't just buy the technology -- the revenue stream has
ongoing value. I expect Cadence will integrate this into their
NC-SIM platform, giving engineers the option of 'e' and (eventually)
System Verilog 3.1a. This removes nearly all of the FUD, so I expect
the longevity of 'e' to greatly increase. This is good news for
companies who have invested heavily in 'e' in the past, further
protecting their legacy code from obsolescence.
And for the vendors? It will be a challenge for Mentor and a disaster
for Synopsys, in my opinion. ModelSim and NC are the two primary HDL
simulators that run under Specman. Undoubtedly Mentor would have
benefited from the demise of Verisity as accounts would have sought
the easiest solution out of the quandary, i.e. drop Specman and
consolidate on the simulator you already have. I think Mentor will
still do well converting ModelSim+Specman accounts to ModelSim+3.1a,
particularly for those accounts that simply want out of the 'e' trap
(beholden to Cadence). Synopsys, on the other hand, has to convince
Specman users to leave both Specman and NC or ModelSim for VCS+3.1a.
Good luck. Many Specman users use VHDL as their HDL, and Synopsys
VHDL support is poor.
I think that this is a particulary bright move by Cadence, as they
will be able to offer existing testbench customers stability and a
roadmap -- and there's good money in that.
- [ An EDA Consultant ]
Medium-good news, because it will encourage more investment in EDA
startups, and because it will mean one less invoice/salesman/
license manager to deal with.
- [ An EDA Consultant ]
Cadence is clearly trying to make some big moves and get back into the
EDA game after falling behind Synopsys and Mentor Graphics. First they
cleared out their top managment and brought in new blood. Now this.
As to for how it affects the EDA world, there are 2 leading HVL's,
Specman and Vera. Cadence did have their own HVL, Testbuilder, but
then for some reason they gave it to OSCI and made it SystemC SCV.
Not sure why. So now they need another HVL, which I guess is why
they bought Verisity.
Like most buyouts, the new company owner has the potential to ruin
a good thing. So its up to Cadence not to mess up Verisity and
hopefully integrate it properly and carefully into their set of tools.
If they keep Verisity as it is, and let them keep doing their own
thing then I think they're OK.
There is some other potential in that, like Synopsys who has Vera
and VCS running together, Cadence could integrate Specman tightly
into NC-SIM. But how well this goes, and how people feel about
Cadence's simulators lately is another story.
- [ An EDA Consultant ]
As an EDA user and Cadence stock holder I think it is another bone head
Cadence move. Cadence has a track record of buying & killing products
and backing the wrong horse. It is inevitable that Vera and Specman
will die in favor of System Verilog just as Verilog and VHDL killed
many of the early HDL's in the 1980's.
The Axis offering overlaps with Quickturn. There is nothing good in
this merger for users or stock holders. Synopsys and Mentor will
dominate the verification market with their support of System Verilog
while Cadence will be eating the Specman table scraps for a few years
and then wonder where their market share went!
- [ An EDA Consultant ]
As a technical consultant who works cheek-by-jowl with users, I would
like to offer you these comments:
1. The acquisition makes sense only if one considers the hardware
verification technology and expertise of Verisity. Its products
complement CDN's high end product, and partially cannibalize it's
overly-expensive low end one, so there is a fit from which users
could benefit (see point 3 below).
2. Verisity's verification tools are based upon a proprietary language
that has never "crossed the chasm". It is still in the hands only
of early adopters. I would expect CDN to "end-of-life" (EOL) these
tools, offering NC-SIM as a replacement. This is bad news for the
convinced early adopters, but not for anyone else.
3. Verisity has been desperately seeking a break out strategy for some
time. Recent attempts to reposition itself as an ESL company - but
with no ESL products (e is not an ESL tool, despite Gartner
assertions to the contrary) - demonstrate just how desperate
Verisity had become. Had the company NOT been acquired, we would
have had to ask how much longer it could have survived on niche
products. In other words, users of its products could have seen an
EOL, anyway. With the takeover, users' investments in expensive
hardware verification are preserved.
Given the above considerations, Verisity was ripe for a takeover, and
CDN paid much too much. However, it does acquire a seasoned management
and engineering team with a track record of innovation in verification,
in marked contrast to CDN's team of Verilog "cow milkers". Of course,
the cows have to be milked, but a farm needs to produce calves that
will produce milk in later years. I would like to see the Verisity
technical management assume management responsibility for all of CDN's
front-end verification, replacing the present lacklustre "leadership".
- [ An EDA Consultant ]
As an EDA user, it's good news. It increases the opportunity to have
e/Specman compete for position on technical merit, without being
burdened by the non-technical problems of being in a relatively small
company without the possibility of being sold as part of larger
tool-flow deals. Verisity were certainly improving on that front, but
the merger is a huge further advance.
Why is letting e/Specman compete on a more level field a Good Thing?
Because the answer to the world's EDA problems isn't an all-singing,
all-dancing, (all-tripping-over-its-own-feet?) System Verilog or
SystemAnythingElse. Not yet anyway. Hard experience is showing that
e/Specman is one of the best verification technologies around. We'll
all be better off if the language wars continue for a while, to let the
candidates show off their respective abilities, and to learn some more
from each other. (Better still, we'll get interoperability solved by a
mechanism more enlightened than language standardisation -- which is
often simply a euphemism for "vendor standardization" -- and then the
language wars can continue even longer. But now I'm dreaming.)
- [ An EDA Consultant ]
My empathy goes to Verisity founders who had to give up their
dream to reality.
This is a good from a user view. Say you have a SOC with
pci-express + 7 other interfaces. You now need a
simulator+Specman+SystemC+pci_express verification component+
the other 7 interfaces
as verification components. This can only be provided by a big
vendor.
- [ An EDA Consultant ]
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