( ESNUG 438 Item 15 ) ------------------------------------------- [01/18/05]
Subject: 14 Users on Specman "e" and System Verilog
> Cadence announced it's buying Verisity for $285 million in cash.
>
> As an EDA user, do you think this is good news or bad news? Why?
I'm a user. I'd say bad news, though actually I've been saying for
about a year and half now. I expected someone would acquire Verisity,
just couldn't see how it could survive the encroachment of SystemC
from "above" and System Verilog from "below."
Why bad news? Currently we're using Specman with Synopsys VCS.
The motivation for both Synopsys and Verisity/Cadence to resolve
Specman issues with Synopsys tools just went way down.
Does it give me real heartburn? No. I have been anticipating
eventually moving to System Verilog anyway.
This merger probably won't help growth of Specman that much, and may
actually retard it. Wouldn't be surprised to see this put some impetus
into the adoption of System Verilog, although System Verilog still has
some holes compared to what Specman can do. Too many built-in
advantages to System Verilog long-term (2-5 years), though. Won't be
like VHDL vs Verilog wars -- both those languages had multiple vendors.
Specman will always have only one vendor.
- [ An Anon EDA User ]
I think it's a good strategy for both Cadence and Verisity.
It completes Cadence's tool flow. Cadence's verification story has
always been particularly weak, but the rest of their verification suite
is pretty strong.
It provides Verisity some industry 'muscle' to keep going. Their
verification tools are best in class, but they've always been
steamrolled by other vendors because of cost and FUD about their
viability.
The two questions that spring to mind is: which emulator do they pick?
and: Do they dead-end 'e' in place of System Verilog?
- [ An Anon EDA User ]
This is very bad because it sets up a possible 'e' vs. System Verilog
verification language war. Along with the existing PSL vs. SVA war,
this would cripple efforts for a consensus on verification standards.
- [ An Anon EDA User ]
Good news for Verisity; so-so for Cadence.
Verisity Specman is going to be replaced by the System Verilog anyway.
Why not make some cash before that happens? Cadence may use Verisity's
people to add the System Verilog feature to NC-Verilog.
- [ An Anon EDA User ]
As an EDA user, I think the Cadence-Verisity merger is a good thing.
Over a year ago, with System Verilog picking up momentum in the same
market, I was wondering what was Verisity's business plan to move
forward.
What Cadence will be doing to Verisity is the same thing Synopsys has
been doing to Vera in the last year and to a lesser extent, what
Mentor Graphics is doing to 0-In. That is taking a good *proprietary*
verification language and morphing it into a *standard based* one:
System Verilog!
As for 'E', well I'm not so sure about it's fate. I think it will be
supported for a couple of years, but with it's future not clear, this
will precipitate the migration to System Verilog.
It is clear that System Verilog is winning. And this is a good thing
for all verification engineers and verification IP companies. All
this new functionality will become part of standard, basic package
under one license. Gone are the days of paying for a simulator, then
paying extra (much more! yuk!) for an HVL.
As for Cadence, I think it also says something about their big push
behind SystemC. I can't say SystemC is dead, there is enough interest
out there to keep it going. But it is clear that Cadence doesn't
think SystemC is the only way to go -- their marketing motto for the
last couple of years! This merger now puts Cadence back in the right
track with them pushing SystemC and System Verilog.
In the end, only gorillas are left standing.
- [ An Anon EDA User ]
Hmmm,
- Cadence has to implement System Verilog (testbench extensions and
all) to compete in the simulator market with Synopsys and Mentor...
- Verisity was working on System Verilog in their simulator, Specsim...
- Cadence buys Verisity.
Can Cadence affort to fund Specman development and System Verilog
development? Something is going to suffer, most likely System Verilog
testbench development.
- [ An Anon EDA User ]
I'm leaning towards bad news. Cadence was the #1 vendor, now they're
even bigger, and Specman "e" could derail our dream of having
integrated design, behavioral modeling, and verification in one
language (System Verilog).
Also, just a year ago Cadence was all about top-down designs starting
with a SystemC architectural model that slowly became all Verilog as
modules were written and verified in the model. If that's still the
case, where does "e" fit in?
If it's not still the case and we're going to be told a story involving
"e" verification at the module level, how can we ever listen to
anything Cadence says again? Not all of us are "lightweight" enough to
change our strategies every year considering some companies have
multi-chip products 3-4 year development cycles.
- [ An Anon EDA User ]
I'd say this is bad news because it will further politicize the
Specman vs. Vera competition. It will probably also delay the
adopton of System Verilog -- I can't see Cadence throwing their
full support to it after spending $285 million for a competitor.
- [ An Anon EDA User ]
As an EDA user, I see this as a natural evolution. This was something
waiting to happen. Cadence needed something better than Testbuilder
to work against Vera.
This may be bad news in another sense. Now instead of System Verilog,
Cadence and Synopsys may fight to keep Vera and Specman alive. That
might be bad news for us.
- [ An Anon EDA User ]
As an EDA user I can't help wonder if this is Superlog all over again.
A lot of good work going down the drain?
On the other hand, standardization of verification languages is good
for the consumer, and I wonder what, if any, impact this merger will
have on this. Synopsys' acquisition of Co-Design bred System Verilog,
which is not exactly standardized either.
- [ An Anon EDA User ]
I don't quite understand how this makes any sense. The move should be
away from proprietary languages (such as Veristy and Vera) and towards
standards such as System Verilog. I would not allow a single line of
testbench code to be written in a language that might not be around.
I think time is up for Verisity and other proprietary languages.
To answer your question, I think this is not good for Cadence and
irrelevant for the rest of us.
- [ An Anon EDA User ]
It seems Cadence will kill Testbuilder and SCV stuff and will
back "e" very strongly. That would negatively impact development
and adoption of System Verilog Testbench. They might have thought
this to be a "single kernel" (built-in) solution to compete with
the already available built-in Native Testbench in VCS. They will
kill SpeXsim and put that technology inside NC-SIM. Not sure how
they will resolve somewhat conflicting emulation (Quickturn) and
hardware accelaration (Axis) products ..
From business ($$ and market share) point of view, obviously,
Synopsys and Mentor have to deal with much bigger and stronger
single competitor in Cadence than two separate entities.
- [ An Anon EDA User ]
This is a non-event for me. Specman, Vera, and TestBuilder will
eventually be replaced by System Verilog, perhaps 5-8 years from now.
Admittedly that is a long time, but the handwriting is on the wall.
- [ An Anon EDA User ]
I have a hard time figuring out why Cadence wants Verisity. Both have
hardware simulators. Both have simulation, code-coverage, and System
Verilog support.
This reminds me of the HP/Compaq merger. I'm not sure what it buys you
except market share.
I like and use Specman. I worry this may mean its ultimate demise.
It doesn't make sense to me that a company would work on two
competing technologies. Will it be Specman or System Verilog? My
bet is System Verilog.
- [ An Anon EDA User ]
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