( ESNUG 437 Item 5 ) -------------------------------------------- [01/11/05]
Subject: Top 30 Keyword Searches on DeepChip for 2004 (part II)
MIND READING: The other way you can read what's on engineer's minds is to
look at the keyword searches they do over the year -- a sort of collective
stream of consciousness. This table is in the format of "keywords"
followed by # of searches. For example, "open access cadence 58" means
that "open access cadence" was searched for 58 times.
11.) Cadence Open Access & Synopsys Milkyway
open access cadence 58
cadence open access 21
open access eda 9
cadence open access database 7
milkyway database open access compatibility 3
open access cadence database 3
open access gdsii 3
eda open access 2
hercules open access 2
oa si2 compilation make open access help 2
open access 2 cadence 2
open access cadence cdba 2
open access database cadence 2
open access hierarchy software free oa 2
synopsys open access 2
aart open access bridge milkyway 1
openaccess database rtl 3
openaccess emh 3
openaccess milkyway 3
cadence openaccess 2
eda database openaccess milkyway 2
openaccess homepage 2
openaccess nc-verilog 2
openaccess netlist convert 2
openaccess opus 2
synopsys milkyway database openaccess 2
milkyway apollo 4
milkyway lef def translator 3
synopsys milkyway 3
.db files in synopsys milkyway 2
astro cap table milkyway apollo synopsys 2
create fram view milkyway 2
gds astro milkyway 2
milkyway api 2
milkyway db 2
milkyway floorplan 2
milkyway gui 2
milkyway lef 2
milkyway lef import 2
milkyway library 2
milkyway metal blockage via pin extraction 2
milkyway synopsys database python 2
milkyway technology files 2
pcell milkyway 2
scheme milkyway apollo 2
synopsys tcl milkyway scheme 2
aart open access bridge milkyway 1
apollo milkyway 1
astro technology file milkyway 1
boa milkyway music download 1
12.) Power & Gated Clocks
power compiler 58
synopsys power compiler 10
powermill tutorial 9
power compiler tutorial 8
hspice leakage power spice file 7
leakage power hspice 6
measure leakage power hspice 5
powertheatre 5
synopsys prime power 5
timing library power compiler 5
avanti star power 4
nanosim leakage power 4
powermill 4
report_power synopsys 4
flow leakage power 4
saif power compiler 4
tutorial powermill 4
current source power rail analysis 3
cynthesizer power 3
definecellinstancepowerbymaster 3
dynamic power analysis 3
floorplan power ir project 3
internal external power rings asic 3
lec power compiler 3
lef def power analysis dc current 3
measuring power with hsim 3
metal layers power strapping 3
metal2 power routing 3
nanosim power measurement 3
power blastrail 3
power compiler clock gating problems 3
power compiler saif 3
power estimation pks 3
power measure 3
power of 2 fifo 3
power-compiler 3
powermill asic tool 3
powermill command list 3
powermill demos 3
prime power synopsys 3
prime power tutorial synopsys 3
primepower nanosim comparison 3
sequence powertheatre 3
.lib power synopsys 2
0.18 memory power ring 2
0.18um power estimation method quick 2
0.25um power plan 2
30% timing library power compiler 2
32-bit as 2.1 memory 4g dell poweredge 2
area clock gating power compiler 2
artisan primepower 2
asic power pad 2
astro rail power analysis 2
astrorail power 2
automatic clock gating for power reduction 2
calibre lvs multi power 2
cell characterization delay power 2
db lib power compiler 2
design compiler report_power 2
eda tools place route power rings 2
esnug primepower 2
floorplan io pad power 2
gated clock power compiler 2
how calibre lvs recognize the power net 2
how to write a dspf file in correct format for power connection 2
hspice leakage power 2
hspice power leakage 2
lef def file format power net 2
level restorer in low power design 2
library power compiler 2
low power eric vittoz 2
magma power compiler 2
max_capacitancepowerpower compiler 2
memorypower compiler 2
modelsim power estimation 2
nanosim power measurement 2
ncverilog power simulation 2
power analyzer schrack 2
power characterization & synopsys 2
power compiler clock gating 2
power compiler clock gating results 2
power compiler scan insertion script 2
power compiler synopsys 2
power compiler synopsys reset 2
power compiler synopsys savings 2
power compiler tcl 2
power estimate 1 million gates 2
power estimation in asic 2
power flow analysis 2
power grid floorplan 2
power grid spice netlist 2
power planning in backend 2
power rail analysis 2
power reduction through rtl clock gating frank emnett 2
power strap calculation asic 2
power supply on a chip laptop 2
power theatre asic 2
power user design flow physopt esnug 2
power wise texas instruments 2
power-compiler power-estimation 2
power_compiler scan dc_shell 2
powerarc power library 2
powermill 5 2
powermill 5x 2
powermill epic 2
powermill leakage synopsys 2
powermill library 2
powermill post 2
powermill posts 2
powermill power theatre magma 2
powermill successful story 2
powermill synopsys 2
powernet electromigration standard cells 2
powerpc cpu verification specman 2
powerpc verification plan 2
powerplanner 2
powerpoint presentation of verilog versus vhdl 2
powersure hdl 2
primepower modelsim 2
primepower spice compare 2
primepower synopsys 2
primepower vhdl naming 2
quick power mentor 2
report_power dc 2
rtl power compiler 2
rtl power estimation in synopsys tool 2
saif power 2
saif power estimation 2
scientific atlanta power 2
silicon ensemble power analysis parasitic 2
simplex power estimation 2
stacked power rings 2
star rc power 2
static leakage power measurement 2
static vs dynamic power analysis 2
statisical power 2
synopsys saif power 2
synopsys .lib file contains timing power model 2
synopsys chrysalis powermill spice 2
synopsys clock gating power compiler toggle insertion 2
synopsys power estimate 2
synopsys power estimation 2
system verilog slides power point 2
systemc low power 2
texas instruments machine reset book for power pro 12 2
timing analysisgated clockspower compiler 2
toggle coverage power analysis 2
toggle rate power consumption 2
vectorless power 2
verilog pli power estimation 2
zia khan power recovery paper 2
power calculation tool boundary scan testing 1
$dumpfile power analysis 1
powermill demo 1
.measure power hspice 1
0.13 power stripes 1
0.13 um power planning 1
0.18um power estimation 1
65nm nand2 power 1
90 nm leakage power 1
accuracy of power compiler 1
adiabatic power supply 1
altera power up problems 1
aluminimum copper power line 1
apache power analysis red hawk 1
arm leakage power 90nm 1
asic power plan 1
asic power planning 1
asic power ring 1
asic power strap 0.18 1
aspen simulator power estimation tool 1
astro power via power grid 1
astro-rail power analysis 1
autologic power upgrades 1
average power computation 1
back annotating primepower 1
gated clock latch 5
avoid gated clock 4
gated clocks 4
module compiler pipeline gated clocks 4
gated clock atpg yahoo group 3
gated clock design 3
deal with gated clock in synopsys 2
formality gated clock 2
gated clock dc_shell 2
gated clock design compile 2
gated clock fpga 2
gated clock glitch 2
gated clock guidelines coding bad 2
gated clock no glitch 2
gated clock power compiler 2
gated clock primetime synopsys 2
gated clock tetramax 2
gated clock problems 2
gated clocks primetime 2
gated clocks lec 2
gated clocks prime time 2
gated negedge clocks 2
infineon gated clock library cell schematic 2
metastability propagated through a nand gate 2
modeltech gated clock 2
primetime gated clock 2
propagated mode ambit 2
synopsys gated clock 2
timing analysis gated clocks power compiler 2
ambit gated clock 1
ambit gated clocks 1
astro gated clock 1
astro gated clocks 1
avoid gated clock hazards fpga -asic 1
13.) Linters
verilint 53
vhdl lint 53
lint vhdl 15
vera lint 13
verilog lint 12
hdlint 11
price of linter 11
verilog linter 10
hdllint 7
surelint 7
verilint warnings 7
free verilog lint 6
spyglass linter 6
verilog linter review 6
everest hdllint 5
hdl lint 5
modelsim lint 5
cheap verilint 4
free verilog linter 4
free vhdl lint 4
interhdl verilint 4
leda lint 4
novas nlint 4
spyglass lint tool 4
synopsys lint 4
everest glint 3
everest verilog glint 3
leda verilint 3
lint tool 3
lint verilog 3
silvaco lint 3
spyglass lint 3
verilint gate level code 3
verilint obfuscate 3
verilint verilog 2000 3
verilog lint review 3
verilog lint tool download 3
black tie lint verification 2
c linting 2
cadence lint tools for hdl design 2
debussy nlint 2
glint verilog 2
glint verilog lint 2
glint verilog rule 2
hdl lint portability rules 2
hdl lint tools 2
hdl linter 2
hdl linting tools 2
hdllint silvaco 2
interhdl verilint acquired 2
leda linting 2
lint debussy 2
lint deepchip 2
lint definition vhdl 2
lint explained vhdl 2
lint group:comp.lang.verilog 2
lint hdl 2
lint option on modelsim 2
lint tools 2
lint verilint interhdl 2
lint vhdl tool 2
lintel 100 vm driver 2
linter price synopsys leda 2
linter verilog 2
linting evaluation 2
linting novas 2
linting tool 2
linting tools tutorial 2
mti lint vhdl 2
nlint 2
nlint compare spyglass 2
nlint pdf 2
nlint review 2
nlint spyglass 2
nova verilint 2
novas nlint license 2
online vhdl linter 2
realintent 2
rtl linter 2
lint 2
sound effects clint eastwood 2
spice netlist linter 2
spyglass lint tool review 2
spyglass linting tool 2
spyglass nlint 2
surefire linting 2
surelint incomplete 2
surelint kill 2
synopsys leda lint 2
synopsys verilint 2
synopsys verilint pricing 2
vera coding rule linting 2
vera linter 2
verilint cost interhdl avanti 2
verilint directives 2
verilint download 2
verilint error messages 2
verilint graphical vg 2
verilint leda 2
verilint pragmas 2
verilint time 2
verilint verilog 2
verilint verilog documentation 2
verilog lint checker lint phil moorby 2
verilog lint 2
verilog lint syntax checker 2
verilog lint tools 2
verilog linter leda 2
verilog vhdl lint tool benchmark 2
verisity surelint pricing 2
vhdl lint free 2
what is lint rtl rule 2
lint vcs option 1
0-in linter 1
altera linter 1
alternatives to verilint 1
avant! verilint 1
avanti verilint 1
benefits of hdl linting 1
atrenta spyglass 5
spyglass leda 5
custom wireload models spyglass 4
spyglass vs leda 4
leda vs spyglass 3
spyglass false path 3
spyglass hdl 3
spyglass tool 3
leda spyglass 2
spyglass asic flow 2
spyglass cad 2
spyglass esnug async 2
spyglass mti 2
spyglass starc 2
spyglass verilog 2
atrenta homepage spyglass 1
atrenta spyglass emacs 1
atrenta spyglass review 1
14.) Delay
set_input_delay 48
set_input_delay set_output_delay 4
input_delay 3
set_input_delay add_delay 3
explain set_input_delay 2
set_max_delay 27
set_output_delay 25
clock insertion delay 18
report_delay_calculation 14
set_min_delay 13
sdf negative delay 11
insertion delay 8
kappa delay line 8
set_annotated_delay 7
arnoldi delay 6
arnoldi delay calculation 6
arnoldi delay model 5
clock to q delay 5
delta delay verilog 5
delta delay verilog modelsim 5
kappa delay lines 5
set_external_delay 5
set_output_delay add_delay 5
verilog delta delay 5
adaptive arnoldi delay 4
crosstalk delay 4
delay_mode_distributed 4
delay_mode_unit 4
insertion delay in primetime 4
intra assignment delays nonblocking 4
modelsim delta delay 4
modelsim delta delay on buffer clock path 4
scalable polynomial delay model 4
set_input_delay set_output_delay 4
clock network delay 4
synopsys set_output_delay 4
vcs negative delay 4
# delay in verilog 3
clock insertion delay lib 3
clock tree insertion delay 3
cmos delay 3
cmos2 delay model 3
delay calculation with detailed parasitics 3
delay calculator 3
delay_mode zero ncelab 3
delay_mode_zero 3
dll early delay line late element 3
input_delay 3
nautilus delay analyzer celestry design technologies 3
negative delay ncverilog 3
negative delay sdf 3
negative delays in nc verilog 3
net delay on ports net delay on internal wires in verilog 3
non linear delay model 3
on-chip variation delays clocks 3
output external delay 3
race condition delta delay 3
scalable polynomial delay model spdm 3
set_input_delay add_delay 3
set_output_delay -min 3
setup hold delay 3
adding buffers for delay to a verilog code 2
back annotating delay 2
calculating interconnect delay 2
carry save delay 2
cell characterization delay power 2
cell delay calculation 2
cell delay si analysis 2
celtic noise sdf delay 2
clk-q delay primetime 2
clock delay timing model vhdl code 2
clock insertion delay pll 2
clock network delay 2
clock pad delay 2
clock tree synthesis insertion delay disadvantage 2
cmos delay library compiler library 2
compile_map_for_delay 2
compute delay time when clock is 100k 2
crosstalk delta transition delta delay 2
delay calculation 2
delay calculation prime time 2
delay calculation star dc 2
delay cell library 2
delay model for bidirectional pins 2
delay prediction in primetime 2
delay sdf script perl 2
delay slew input output cell 2
delay statement cause race condition 2
delay_mode 2
delay_mode ncverilog 2
delay_trigger verilog 2
design compiler how to calculate delay 2
designware multiplier delay 2
explain set_input_delay 2
hlo_minimize_tree_delay 2
insertion delay clock tree 2
insertion delay scan enable 2
intra assignment delays in verilog 2
intrinsic delay 2
kappa company delay 2
kappa delay devices 2
magma awe delay 2
max_delay synopsys 2
miller effect delay 2
multiple clocks set_output_delay synthesis 2
nautilus delay analyzer 2
ncelab delay_mode 2
ncelab negative delay 2
ncverilog delay_mode_unit 2
ncverilog mode_delay_zero 2
negative delay in sdf 2
netlist simulation vcs sdf delay 2
ocv delay 2
output_delay 2
path delay test tetramax approach 2
pearl delay interconnect 3d model hyperextract 2
pll clock insertion delay 2
pll for clock insertion delay 2
primetime clock network delay 2
primetime delay calc 2
primetime negative delays 2
primetime net delay calculation 2
primetime output delay 2
primetime path delay 2
propogation delay calculator 2
propogation delay example 2
rc delay 2
report_timing -delay min 2
running vcs with annotated sdf delays 2
scalable polynomial delay 2
sdf delay calculator 2
sdf delay calculator layout 2
sdf delay files 2
sdf min typ max delay 2
set_input_delay -clock 2
set_input_delay -min 2
set_input_delay <> 2
set_input_delay negative 2
set_input_delay network insertion delay 2
set_input_delay on a pin 2
set_input_delay path delay 2
set_input_delay setup hold 2
set_input_delay timing diagram 2
set_input_delay two paths 2
set_max_delay cliff 2
set_max_delay set_input_delay 2
set_max_delay syntax 2
set_max_delay virtual clock synopsys 2
set_min_delay hold 2
set_output_delay min 2
set_output_delay minus 2
set_output_delay negative values 2
set_output_delay on multi clock 2
set_output_delay reference 2
set_output_delay syntax 2
set_output_delay what is 2
should i use a delay for rtl simulation 2
specify unit delay ncverilog 2
static timing analysis sta delay slope slew transition time cell 2
synopsys liberty 3 dimensional delay table 2
synopsys sdc cts insertion delay 2
synopsys set_output_delay syntax 2
synopsys timing library model delay calculator 2
tetramax delay test 2
tf_setdelay 2
timing report -delay max synopsys 2
transistor delay modeling nassda 2
transition delay 2
use delay cell 2
vcs delay_mode_unit 2
vcs negative delays 2
vcs zero delay 2
verilog 1 delay 2
verilog ifdef unit_delay 2
verilog negative delay support 2
verilog negative time delay calculation 2
verilog sdf port delays 2
vim syntax file sdf standard delay format 2
virtual clock set_max_delay 2
what is clock tree insertion delay 2
why is min delay best for hold time 2
wire .18 um delay estimation 2
wire delay .18 um 2
zero unit delay sdf ncverilog 2
sdf delay calculation purpose 1
#delays in rtl code 1
- add_delay 1
.scr set_input_delay 1
.sdf delay 1
3d delay 1
delay_mode_distributed 1
accnodelay 1
add delay in cshell script 1
add_delay 1
add_delay input_delay output_delay 1
adding clock delay 1
adding delays on rhs 1
analog artist calculator delay 1
annotate delay 1
annotated sdf with delay 1
annotating delays at rtl 1
apollo 9 delay 1
apollo sdf extraction minus delay 1
appologize for delay 1
arnoldi delay calculate 1
arnoldi delay model elmore delay model 1
arnoldi delays 1
arnoldi elmore delay 1
asic delay lines 1
atpg delay fault 0.18u 1
awe delay avanti 1
back annotation delays 1
15.) Verisity Specman e
specman e 47
vera specman 19
specman tutorial 18
vera vs specman 17
specman e language 14
specman 10
specman coding guidelines 10
specman versus vera 10
specman vs vera 10
specman jobs 9
specman tool 9
specman elite tutorial 8
e language specman 7
specman e tutorial 6
specman license 6
specman training 6
vericity specman 6
difference between specman-e vera 5
specman e-code examples 5
specman examples 5
specman interview questions 5
specman user group 5
vera versus specman 5
aspect oriented programming specman 4
compare specman vera 4
e specman 4
especman 4
learning specman 4
reading process id specman 4
specman crack 4
specman job 4
specman overview 4
difference between vera specman 3
doxygen specman 3
learning vera specman in singapore 3
specman coding 3
specman e code 3
specman e vera 3
specman elite crack 3
specman emacs 3
specman evaluation demo 3
specman language 3
specman language book 3
specman mode emacs 3
specman set variable from command line 3
specman users group 3
specman vera 3
specman vera comparison 3
specman vs verilog 3
systemc specman 3
vera specman compare 3
vera specman comparison 3
write good specman e 3
advantages of using specman based random verification 2
basics of specman verification tool 2
compare between vera specman 2
denali specman ddr 2
difference between verilog test bench specman 2
dresden specman 2
e language hdl example explanation specman 2
e specman learning 2
e/specman 2
fusion specman 2
how to access verilog memory in specman? 2
interface perl specman explain 2
linking specman with modelsim 2
linux specman vera 2
market share specman vera 2
mixed signal specman commands 2
modelsim specman link 2
ncverilog specman 2
powerpc cpu verification specman 2
psl specman comparison 2
random verification in specman 2
sean smith specman 2
signal mapping vhdl verilog specman 2
specman & systemc 2
specman & xilinx & mentor 2
specman and vera 2
specman c interface 2
specman c language slow 2
specman constructor 2
specman disadvantages 2
specman e for windows 2
specman e language examples 2
specman e manual 2
specman e training 2
specman e user guide 2
specman e vera software 2
specman e yahoo user group 2
specman e-code 2
specman elite verification 2
specman germany chip 2
specman ieee 2
specman introduction 2
specman license cost 2
specman montreal 2
specman object orientated 2
specman out of memory 2
specman reset 2
specman save restore 2
specman synopsys 2
specman testbench 2
specman testbuilder vera 2
specman to vera conversion 2
specman tutorial verification 2
specman tutorials 2
specman university price 2
specman user manual 2
specman vcd 2
specman vera compare 2
specman vera system verilog 2
specman vera testbuilder 2
specman vericity 2
specman verilog comparison 2
specman verisity 2
specman verisity stratus 2
specman vhdl 2
specman vi tool 2
specman vs conventional verification methodologies 2
specman vs e verification language 2
specman vs. vera 2
specman wave 2
specman/e 2
specman; cons 2
system verilog specman snug 2
system verilog vera e systemc specman 2
systemc vera specman 2
temporal in specman e language 2
track specman script 2
vera specman verification presentation 2
vera synopsys specman 2
vericity specman elite 2
verisity specman 2
verisity specman e 2
verisity specman e vera testbench cae 2
vlsi verification tool specman e vera 2
what is specman tool 2
what's specman/e 2
0-in specman comparison 1
actor jeff specman 1
aop specman e 1
architecture coverage using specman 1
asynchronous reset specman 1
atm specman 1
book specman 1
books on specman 1
books on specman e language 1
books on specman e-language 1
verisity market share 4
verisity synopsys 4
eric owens verisity 3
safelogic vs verisity 3
verisity e tutorial 3
c e verisity 2
coverage maximizer verisity 2
e language verisity 2
einstein problem verisity 2
epl verisity 2
esnug verisity verilog simulator 2
janick bergeron verisity 2
verisity deepchip 2
verisity e tutorial 2
verisity epl 2
verisity platform division axis systems 2
verisity sucks 2
verisity surelint pricing 2
verisity text editor 2
verisity tutorial 2
2000 dataquest verisity 1
amos noy verisity 1
16.) Random Number Generators
vhdl random 61
vhdl random number generator 46
vhdl random number 35
random number generator vhdl 34
verilog $random 19
verilog random 19
vhdl random numbers 18
vhdl random generator 15
random number vhdl 11
random number generator verilog 10
vhdl random function 10
random number generator vhdl code 8
verilog random number generator 8
random generator vhdl 5
random number generator in vhdl 5
random number verilog 5
random numbers vhdl 5
verilog $random task 4
verilog random number 4
verilog randomize 4
vhdl random integer 4
vhdl random package 4
dist vera random 3
random function in vhdl 3
random number generation in vhdl 3
random number generator in verilog 3
random number in vhdl 3
random vhdl 3
synopsys $random 3
verilog $random syntax 3
abel pseudo-random number generator 2
advantages of using specman based random verification 2
audit your design to avoid the random testing nightmare 2
characteristics of memorandom 2
design vhdl random number generator 2
flowchart for generate pseudo random numbers 2
help vhdl random number generator 2
pli random 2
pseudo random logic bist mentor 2
random code gobble gook 2
random function vhdl 2
random number generation using vhdl 2
random number generator vhdl code .vhd .vhdl 2
random number generator vhdl example 2
random number use vhdl 2
random verification in specman 2
random vhd 2
synopsys random seed dc_shell 2
verilog module endmodule random stimulus coding examples 2
verilog module random stimulus coding examples 2
verilog random task 2
versity vera random 2
vhdl code for generating random numbers 2
vhdl function random 2
vhdl generator number random 2
vhdl random bit generator 2
vhdl random data generator 2
vhdl random library 2
vhdl random routine 2
$random ncverilog 1
$random seed vhdl sample code 1
$random verilog use 1
4 bit vhdl random number generator 1
5-bit random counter verilog 1
17.) SystemC, Forte, & PrecisionC
precisionc 45
mentor precisionc 13
precisionc mentor 11
precisionc opinion design 2
precisionc tool 2
rtl synthesis precisionc 2
systemc examples 33
systemc example 23
systemc tutorial 22
modelsim systemc 20
systemc.h download 18
systemc 17
system verilog systemc 14
systemc compiler 14
systemc synthesis 11
systemc freeware 10
systemc counter 9
verilog to systemc 8
vhdl to systemc 8
systemc tools 7
free systemc compiler 6
system verilog vs systemc 6
systemc benchmark 6
systemc modelsim 6
systemc newsgroup 6
systemc to vhdl 6
systemc vera 6
forte systemc 5
free systemc simulator 5
systemc adder 5
systemc hp.com 5
systemc sucks 5
systemc systemverilog 5
systemc verilog 5
systemc.h 5
vcs systemc 5
verilog systemc cosim vcs 5
doxygen systemc 4
synopsys cocentric systemc tutorials 4
synopsys dc_shell systemc manual 4
synopsys systemc compiler 4
systemc compiler freeware 4
systemc cosim 4
systemc memory leak 4
systemc simulator 4
systemc system verilog 4
systemc to rtl 4
systemc visio 4
vera systemc 4
compile_systemc fpga 3
download systemc.h 3
esnug 412 systemc 3
hdl2systemc 3
if- else statements in systemc 3
cooley systemverilog systemc 3
pullup logic in systemc 3
starkey systemc 3
synthesize systemc 3
systemc code example 3
systemc downloads graphic free 3
systemc doxygen 3
systemc group:comp.* 3
systemc gui 3
systemc performance 3
systemc pros cons 3
systemc scv 3
systemc segmentation fault 3
systemc specman 3
systemc translator 3
systemc tutorial forte 3
systemc vcs 3
systemc vs system verilog 3
systemc vs vhdl 3
systemc vs. vhdl 3
why use systemc 3
advantages of systemc over other hdls 2
andrew goodrich systemc 2
andy goodrich systemc 2
art de geus systemc 2
behavioral compiler systemc 2
behavioral synthesis systemc freeware 2
best systemc book 2
bit manipulation systemc code 2
cadence systemc compiler pli call 2
cadence systemc lay-off 2
cadence systemc rumor 2
carbon design systemc 2
clock in systemc 2
compare system verilog systemc 2
converting c to systemc 2
cossap systemc verilog 2
counter with d flip-flops in systemc 2
dumping signals systemc 2
emacs systemc 2
example systemc 2
forte systemc compiler 2
forte systemc free tutorial 2
forte systemc japan andy 2
forte systemc to rtl 2
free systemc tutorial 2
freeware systemc editor 2
freeware systemc synthesis tool 2
generate statement systemc 2
graphic systemc 2
license file systemc compiler hack 2
max plus ii vs systemc 2
nc-sim systemc 2
novilit systemc 2
opinion mixed language systemc simulator performance 2
optimizing systemc library 2
osci systemc hooks to modelsim 2
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18.) SPEF, DSPF, LEF, DEF, PDEF
spef format 44
spef file format 12
spef syntax 10
spef dspf 7
spef parasitics 7
spef format syntax 6
spef hsim 6
spef stitch 5
primetime hierarchical spef 4
read_spef 4
spef timing 4
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.spef format 2
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multi spef hold timing analysis 2
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spef extraction 1
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dspf syntax 6
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.dspf .set load 1
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lef syntax 17
lef file 13
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lef/def 9
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def to verilog 8
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cadence def 3
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astro def netlist 2
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19.) Cadence CDL
cdl netlist 43
verilog2cdl 7
cdl spice 6
edif to cdl 6
spice to cdl 4
verilog to cdl 4
cadence cdl import 3
cadence import cdl 3
cdl cadence 3
cdl format 3
cdl lvs 3
cdl to spice 3
cdl to verilog 3
import cdl cadence 3
spice cdl 3
cadence cdl export 2
cdl example cadence 2
cdl export template file cadence 2
cdl format netlist 2
cdl netlist .v 2
cdl netlist edif converter 2
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spice to cdl netlist 2
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*.connect cdl spice lvs 1
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.gds .lib .cdl 1
20.) Hold & Setup
hold time violation 43
$setuphold 38
setup hold time violations 20
setuphold 20
hold time violations 14
set_fix_hold 14
fixing hold time violations 12
$setuphold verilog 9
verilog $setuphold 9
negative hold time 8
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negative hold ncverilog 6
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hold time fix 5
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fix hold violation 4
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set_multicycle_path hold 4
set_multicycle_path setup hold 4
set_test_hold 4
setup time hold time 4
setuphold sdf vcs 4
slew_lower_threshold_pct_fall 4
synopsys script fix hold 4
bus holder vhdl 3
correct setup violations hold violations 3
fix hold time 3
fix hold time violation 3
hold time calculation flop tcl script 3
hold time violation fixing 3
hold time violation synopsys 3
how to check hold time violation 3
how to fix hold time violation 3
magma hold script eco 3
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on chip variation hold time 3
output_threshold_pct_fall 3
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setup hold delay 3
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setup hold time 3
setup hold timing 3
setup hold violation 3
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$setuphold check 2
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setup time violation 16
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