( ESNUG 433 Item 7 ) -------------------------------------------- [10/20/04]
From: Premysl Vaclavik <premysl.vaclavik=user domain=ondemand.co.at>
Subject: Premysl's Detailed Magma Blast Create & Blast Fusion Tapeout
Hi John,
In case you are still collecting the tapeout stories this is one about our
flow with Magma.
We used Blast Create for the synthesis, Blast Fusion for the P&R and
BlastRail for the power and rail analysis. The final GDS merge, DRC and
LVS were done using IC Graph and Calibre. Process was .13 um Chartered.
We have started the design on the SunUltraAx machines but switched after
a short time to Linux based PCs. They were simply much faster.
Libraries:
Magma support created the first Volcano database of the standard cell
library for us. Later we created the I/O Volcano database as well as
the memory libraries ourselves. As we started to learn the tool more,
we were able to implement additional rules for P&R and antenna. At the
end we were able to write the scripts in MTcl which we used to generate
the new version of the libraries.
Blast Create synthesis:
We had a 2-day crash training for the Blast Create (RTL and DFT) held in
our design center. After that, we were able to start with the help of
their phone support to do the first steps of a design. We started with
version 4.0.19 and finished with version 4.0.36. Blast Create was able
to read both VHDL and Verilog, but because our design is in pure VHDL,
we used the VHDL import functions only.
At the beginning we had some concerns about the memory requirements of
Blast Create synthesis. It was about 2.4 GB for one submodule! This
problem was fixed by Magma support within one week. Unfortunately their
synthesis speed then decreased, too.
We also discovered one RTL/netlist mismatch, which was fixed again within
8 days, with Magma R&D worked over the weekend. As their 32-bit version
has a 4 GB memory limit, we checked the 64-bit version of Blast Create
running under Linux on an Opteron computer, but finally we did not need
to switch to 64-bit, because we kept design within a 3G RAM.
Gotchas:
- VHDL parser messages should give more information
- Missing on-line explanation for the error/warning codes
- Can not handle VHDL modules with same name, existing in different
VHDL libraries.
- The .volcano database structure requires strictly unique name space
for all modules in any library.
Blast Fusion P&R:
All Blast tools use the common design database (.volcano) throughout the
whole design flow from RTL to GDS. The common timing engine is used at
all design steps, without any need for data exchange to external tools.
Parasitic extraction, crosstalk and noise analysis are integrated in the
standard design flow and are called by simple Mtcl commands. For ECOs,
we were able to re-spin our design at any design step. Even at the
finalization stage we were able to handle RTL design fixes.
Computer: 2.8GHz, Pentium4, Linux, 3 GB RAM
fix fix fix fix fix fix
rtl netlist time cell clock wire cleanup post-fix
----- ------- ------ ----- ------ ----- ------- --------
00:28 00:52 03:06 08:42 01:48 08:18 01:12 01:06
524 MB 740 MB 1243 MB 1574 MB 1506 MB 1980 MB 1855 MB 2585 MB
The most time consuming task was the creation of a good floorplan and
power planning. We used the MTcl scripts to describe it and the GUI was
used just for the visual checks. We have tried to keep the software always
running in a batch mode and to use the interactive mode only if necessary,
because we were limited in a number of licenses.
We made some experiments with manual placement using placement clusters,
but we got the best results just by the controlling the placement through
proper floor and power planning. We have run their clock tree synthesis
with the crosstalk option and the tool made a good job there.
Their rail analysis tool gave us good reports about the IR drop in the power
mesh, so we were able to fix the supply problems very quickly. We were not
licensed to use their IR drop induced delay analysis feature, so we had to
rely on our experience from the previous designs.
There is a good support for metal slotting which also splits a via array,
but we have used it just in an outer power ring to have better control over
the slot space.
After our first P&R runs we had to fix the M1 rules in the library because
there were design rule violations which were not recognized by Blast Fusion
but reported by the Calibre design rule checker. We had to also modify the
cumulative antenna rule description in the .volcano library to conform with
the runset and the design rule manual provided by Chartered.
At the end we had 2 design rule violations indicated by Blast Fusion and
had to fix them by hand in a layout editor. The antennas were fixed by
Blast Fusion without including any diode.
Their signal integrity flow needed a bit more runtime as expected, but the
crosstalk delay fix was done without any problem. Our routed design passed
final LVS without any mismatch between the netlist and extracted netlist.
We have also checked the RTL against the reference netlist using
FormalPro, so we were quite confident the netlist is correct.
Blast Fusion has no print/plot support and their on line man page search
engine is insufficient.
We received the first Blast Create training in October, 14-15 2003 and had
a tapeout in January 23, 2004.
- Premysl Vaclavik
On Demand Microelectronics Vienna, Austria
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