( ESNUG 432 Item 7 ) -------------------------------------------- [08/25/04]
From: Colin Macdonald <c.macdonald=user domain=freescale spot calm>
Subject: Using PrimeTime-SI, PhysOpt, and Astro to Address Crosstalk Delay
Hi John,
My colleague Anis Jarrar and I have developed a "signal integrity aware"
timing closure methodology that's been used successfully on a number of
0.13u SoCs here at Freescale Semiconductor. Although this methodology
addresses both crosstalk delay and crosstalk noise, we'd like to describe
in some detail our approach to crosstalk delay -- which we have found to
present the greater challenge.
We used PrimeTime-SI to automatically analyze failing data paths in detail
to generate a list of tailored fixes:
1) cell upsizing for setup violations
2) delay cell insertion for hold fixes
3) wire repels for setup and hold violations
The cell upsizes and insertions that were written out from PrimeTime-SI
were implemented via Design Compiler. Astro constraints files, generated
by PrimeTime-SI, were used to implement wire-repels both automatically and,
in the very last stages, manually.
Crosstalk can only be fully addressed during or after detailed route, which
is late in the design flow and typically a crunch period. Chip-level
netlists and parasitic files are large and time consuming to get in and
out. Until synthesis and physical design tools become fully SI aware, the
disconnect between SI measurement and fixing means that fixes may either
not work, not work fully or may cause other problems.
Preventing Crosstalk Delay In Layout:
Astro-Xtalk provides crosstalk and noise analysis. While its timing window
and other delay calculations were not quite as accurate as PrimeTime-SI, we
still employed Astro-Xtalk to reduce the initial size of our crosstalk
problem. However, in order to meet our aggressive timing goals, we also
used PhysOpt for placement.
We had specific polices for the design of clock and asynchronous networks.
Additionally, we established new floorplan guidelines for our designers.
1. Clock Networks.
We've found that double/triple spacing clock network tracks and routing
clocks on reserved metal layers is very effective in eliminating
crosstalk on clock networks. Clock networks (and other high fan-out
nets) have many levels of logic. Each receiver in a clock tree network
can incur a small crosstalk delta that by itself is negligible.
However, when these delays are summed from clock source to destination
the total delta can be more than large enough to cause a significant
violation.
The PT "timing_remove_clock_reconvergence_pessimism" allows your timing
contributions from common portions of the clock tree to be eliminated.
This variable can usually be set to true, especially for min delay
timing, when the launch and capture clocks are coincident.
When a timing violation is caused by many small crosstalk components
(such as on a clock tree) then fixing the violation can be difficult.
Even if the fix is successful, your design may be significantly
perturbed. So, for clock networks in particular, prevention is better
than fixing.
2. Non-Clock Networks.
Double/triple spacing, shielding and the utilization of reserved metal
layers work well for clocks and other high fanout nets, but these
approaches can frequently be too costly for other types of structures,
such as reset networks. An alternative approach for these networks,
(particularly asynchronous reset networks where crosstalk noise
glitches can cause register contents to change) is to eliminate the
use of low drive cells. Our methodology uses higher drive strength
cells in the reset network. This raises the threshold for would-be
aggressors and thereby reduces the vulnerability and number of
victim nets.
3. Floor Planning.
We spent more engineering time in floorplanning, specifically in the
area of congestion reduction, because crosstalk occurs when aggressor
and victim nets are in close proximity. One benefit of this was that
Astro had less SI violations to fix and was able to fix those
more easily.
Our experience has been that while "standardized" power grids may
require less engineering time to develop, the fact that they are over-
designed reduces routing resources for the SoC. This can lead to
more SI problems later in the flow. So, we established an approach of
spending more time during floorplanning to create power grids that do
not overly reduce routing resources.
Preventing Crosstalk Delay In Synthesis:
There are measures that can be taken during the physical synthesis of your
netlist and the generation of clock or reset trees.
1. Setting the max_transition time DRC in Design Compiler to 1 nsec or
less for 0.13 um designs. The max_transition value can be reduced
further for PhysOpt, say 750 psec, when net characteristics are better
known. Setting a max_transition value lower than the library default
helps reduces the number of potential victims.
2. Guardbanding for setup and hold times. During non-SI aware synthesis,
you can't predict how an individual timing path will be affected by
crosstalk. However, we do know that paths with less slack are easier
to turn into violations, so we guard band non-SI setup and hold timing
to reduce the number of crosstalk induced violations. While guard
banding like this can lead to an increase in gate count, the benefits
were a reduced number of cross-talk induced timing violations.
3. Clock tree synthesis for high fanout networks. We try to use only high
drive strength buffers, particularly for networks that are isolated;
for example reset trees. Larger drivers makes the receivers less
susceptible to victimization and should also reduce the number of
driver-receiver segments. Fewer segments means less opportunity for
SI effects and mean fewer contributions to a summed crosstalk delta.
Two Scripts For Verifying Prevention Measures:
Since prevention may not work as planned and something may go wrong in the
design process, it's good to be able to check the results of prevention
measures. To check the results of our preventive methods, we developed
two PrimeTime-SI procedures that write the crosstalk contributions to
delay on the clock tree network to a file.
In addition to the min/max rise and min/max fall contributions, our
procedures also write out the differences between min and max
contributions. The output file can be sorted according the data in any
of the columns allowing problems to be easily identified.
These procedures, Check_Net_For_Xtalk and Check_Clock_Network_For_Xtalk,
are shown below.
Note: One recently found limitation of these two scripts is that the clocks
should be defined on cell pins and not hierarchical boundaries.
A. CHECK_NET_FOR_XTALK - Reports Crosstalk Contribution On A Supplied Net
# CHECK_NET_FOR_XTALK
# Colin MacDonald/Anis Jarrar, Freescale Semiconductor, July 2004
# Summary: Reports Crosstalk Contribution On A Supplied Net to
# a Supplied File Handle
# This routine is called by check_clock_network_for_xtalk
# Note: type check_net_for_xtalk -help for information
# EXAMPLE USAGE:
# set ofid [open Report_Test.rpt "w" ]; # Open/create report File
# set oiid [open Info_Test.rpt "w" ]; # Open/create info File
# check_net_for_xtalk "[get_net DUT0/clkfast_core__L5_N0]" \
# -Report_FID $ofid -Info_FID $oiid; # First net supplied
# check_net_for_xtalk [get_net DUT0/clkfast_core__L4_N0] \
# -Report_FID $ofid -Info_FID $oiid; # Second net supplied
# close $ofid; # Close output file
# close $oiid; # Close information file
proc check_net_for_xtalk { args } {
parse_proc_arguments -args $args p_args
if {[info exists p_args(-Report_FID)]} {
set rep_fid $p_args(-Report_FID)
}
if {[info exists p_args(-Info_FID)]} {
set inf_fid $p_args(-Info_FID)
}
if {[info exists p_args(one_net)]} {
set i_net $p_args(one_net)
}
set process true
set wir_nam [get_attribute $i_net full_name]
set out_pnz [filter_collection [get_pins -of_objects $i_net ] \
"direction == out" ]
set siz_out [sizeof_collection $out_pnz ]
if {$siz_out != 1 } {
set process false
puts $inf_fid \
"INFO: Ignoring net $wir_nam drivers = $siz_out"
}
if { $process } {
set out_nam [get_attribute $out_pnz full_name ]
set inp_pnz [filter_collection [all_fanout -from \
$out_nam -flat -pin_levels 1 ] "object_class == pin" ]
set inp_pnz [remove_from_collection $inp_pnz $out_pnz ]
set siz_inp [sizeof_collection $inp_pnz ]
if {$siz_inp == 0 } {
set process false
puts $inf_fid "INFO: Ignoring net $wir_nam no receivers "
}
if { $process } {
foreach_in_collection i_inp $inp_pnz {
set inp_nam [get_attribute $i_inp full_name]
set inp_lpn [get_attribute $i_inp lib_pin_name ]
set tac [get_timing_arc -from $out_nam -to $inp_nam ]
set siz_tac [sizeof_collection $tac]
set dlt_mnf [get_attribute $tac annotated_delay_delta_min_fall]
set dlt_mxf [get_attribute $tac annotated_delay_delta_max_rise]
set dlt_mxr [get_attribute $tac annotated_delay_delta_max_rise]
set dlt_mnr [get_attribute $tac annotated_delay_delta_min_rise]
set dif_ris [expr abs ([expr $dlt_mxr - $dlt_mnr ])]
set dif_fal [expr abs ([expr $dlt_mxf - $dlt_mnf ])]
set dif_wst $dif_fal
if { $dif_ris > $dif_fal } { set dif_wst $dif_ris }
if {($dif_ris != 0) || ($dif_fal != 0) } {
set xtalk_string "XTALK: $wir_nam $out_nam $inp_nam"
puts $rep_fid [format "%s %1.7f %1.7f %1.7f %1.7f %1.7f" \
$xtalk_string $dlt_mxr $dlt_mnr $dlt_mxf $dlt_mnf $dif_wst ]
}
}
}
}
}
define_proc_attributes check_net_for_xtalk -info "
Description:
Analyzes a supplied net for crosstalk contributions. Finds a driver
pin connected to the net and all receivers of the driver pin.
Determines crosstalk contributions on all driver-receiver timing
arcs. Outputs results to a writable file specified by report file
id argument (-Report_FID) and processing info to writable file
specified by info file id argument (-Info_FID). Note that the report
file can be sorted by any column & the nets with largest crosstalk
problems can be easily identified.
Report File Format:
XTALK: net_name driver_pin receiver_pin (cont..)
(...cont) xtalk_max_rise xtalk_min_rise (cont..)
(...cont) xtalk_max_fall xtalk_min_fall (cont..)
(...cont){ bigger of |xtalk_max_rise - xtalk_min_rise| (cont..)
(...cont) and |xtalk_max_fall - xtalk_min_fall| }
Command Line Usage:
check_net_for_xtalk -define_args { \
{-Report_FID "Report File ID, file must be open and writable" \
"rep_fid" string required} \
{-Info_FID "Info File ID, file must be open and writable" \
"inf_fid" string required} \
{one_net "Net for xtalk analysis" "one_net" list required}}
"
B. CHECK_CLOCK_NETWORK_FOR_XTALK - Reports Crosstalk on Clock Tree Network
# PROCEDURE CHECK_CLOCK_NETWORK_FOR_XTALK
# Colin MacDonald/Anis Jarrar, Freescale Semiconductor, July 2004
# Summary: Reports Crosstalk on Clock Tree Networks
# This routine opens a report file for results and a information
# file for run time issues.
# The script also creates a collection of nets that are supplied to
# the procedure check_net_for_xtalk
# Note: type check_clock_network_for_xtalk -help for information
# EXAMPLE USAGE:
# check_clock_network_for_xtalk -Version test -STA_Mode Functional \
# -PVT_Case Best -Output_Dir .
proc check_clock_network_for_xtalk { args } {
parse_proc_arguments -args $args p_args
set net_vrs "VRS_xxx"
if {[info exists p_args(-Version)]} {
set net_vrs $p_args(-Version)
}
set sta_mod "MOD_xxx"
if {[info exists p_args(-STA_Mode)]} {
set sta_mod $p_args(-STA_Mode)
}
set pvt_cse "PVT_xxx"
if {[info exists p_args(-PVT_Case)]} {
set pvt_cse $p_args(-PVT_Case)
}
set rep_dir "."
if {[info exists p_args(-Output_Dir)]} {
set rep_dir $p_args(-Output_Dir)
}
set ofidl [open \
${rep_dir}/clk_xtalk_${net_vrs}_${sta_mod}_${pvt_cse}.rpt w+]
set oiidl [open \
${rep_dir}/clk_xtalk_${net_vrs}_${sta_mod}_${pvt_cse}.inf w+]
set clk_trz [get_nets -of_object [ all_fanout -clock_tree -flat ]]
set inc 0
echo -n "INFO: Analyzing Clock Tree Network For XTALK Delta "
foreach_in_collection i_net $clk_trz {
set inc [expr $inc + 1]
check_net_for_xtalk $i_net -Report_FID $ofidl -Info_FID $oiidl
if { $inc == 25 } { echo -n "\b\b||" }
if { $inc == 50 } { echo -n "\b\b//" }
if { $inc == 75 } { echo -n "\b\b--" }
if { $inc == 100 } { echo -n "\b\b\\\\" ; set inc 0 ; }
}
echo "\b\b "
close $ofidl
close $oiidl
}
define_proc_attributes check_clock_network_for_xtalk -info "
Description:
Analyzes all clock networks for crosstalk contributions.
Outputs results to report file and runtime information to info file.
Command line optional args are used to name & place output files.
Report File = \
{Output_Dir}/clk_xtalk_{Version}_{STA_Mode}_{PVT_Case}.rpt
Info File = \
{Output_Dir}/clk_xtalk_{Version}_{STA_Mode}_{PVT_Case}.inf
If an argument is not given, it's default value is used for the file.
For example, if no arguments are supplied the report file will be
./clk_xtalk_VRS_xxx_MOD_xxx_PVT_xxx.rpt.
Report File Format:
XTALK: net_name driver_pin receiver_pin (cont..)
(...cont) xtalk_max_rise xtalk_min_rise (cont..)
(...cont) xtalk_max_fall xtalk_min_fall (cont..)
(...cont){ bigger of |xtalk_max_rise - xtalk_min_rise| (cont..)
(...cont) and |xtalk_max_fall - xtalk_min_fall| }
Command Line Usage:
check_clock_network_for_xtalk" \
-define_args { \
{-Version "Netlist version, default VRS_xxx " \
"net_ver" string optional} \
{-STA_Mode "STA timing mode e.g. FUNC or SCAN, default MOD_xxx" \
"sta_mod" string optional} \
{-PVT_Case \
"Process, voltage, temeperature identified, default PVT_xxx" \
"pvt_cse" string optional} \
{-Output_Dir \
"Writable directory for output files, default is current dir" \
"rep_dir" string optional}}
"
Repairing Crosstalk Delay:
Despite our best efforts at prevention, we will get crosstalk delay induced
violations and so we need to fix them.
1. Crosstalk Repair Flow
We iterate on a non-SI flow until there is suitably close to zero
negative slack, and then perform STA using PrimeTime with SI enabled.
If we have negative slack, we generate fixes. In fact, we generate
two types of fix files. An Astro Scheme script, generated by
create_astro_xtalk_constraints (for net repelling) and a write_script
format file containing cell insertions and upsizes.
The Astro Scheme script output is used to either automatically
generate net repels or, in the final stages of timing closure, to
direct manual net movement. The output from Astro is ultimately a
new parasitic file that is used to check the effect of the fixes.
The write_script output includes design changes that we estimate would
minimize crosstalk induced delays. This includes cell upsize change
(increased drive strength) determined from the max delay analysis and
delay cell insertions determined from the min delay analysis. The
write_script file can either be read back into PrimeTime-SI to check
the suggested fixes will eliminate the crosstalk induced delay or used
by Design Compiler to generate a new fixed netlist. The wire repel
and netlist update loops are used as often as required to get zero
negative slack. A user defined variable in the PrimeTime-SI scripts
is used to control the ratio of fixes generated by each method.
While netlist changes are possible, we place more emphasis on netlist
updates. As our tolerance for netlist changes drops towards tape out,
we place more emphasis on net repels. Once netlist changes are
prohibited we must exclusively rely on net repels. In fact, for those
of us who like to live on the edge, it's possible to start shipping
lower mask layers, such as poly or active, while wire fixing is being
carried out on the metal layers!
2. PrimeTime-SI for Analysis
To reduce the size of our crosstalk problem when running PrimeTime-SI,
we execute PrimeTime in two steps. The first step is with the SI
option disabled, and our design is checked for all timing violations.
Because SI is disabled, the computer processing time is quick (with SI
enabled, static timing analysis, STA, is significantly slower). After
the chip or block close to 100% timing error free, we perform
PrimeTime-SI timing analysis.
- Performance Issues. Enabling SI in PrimeTime can increase runtime
and memory usage significantly. Fortunately, we found effective
steps to monitor and manage this. First, we increase visibility
of a session's memory footprint and CPU usage by inserting "mem"
and "cpu" commands at strategic points throughout their scripts.
Second, we obtain detailed progress on report generation and timing
updates by setting variables timing_update_status_level and
timing_report_status_level to high. Memory footprints can grow by
up to 2x, so large designs may require a 64-bit version of
PrimeTime-SI. Timing updates take much longer than with SI
disabled and should be minimized at all costs. Prior to release
2002.09, two timing updates were required to make clock networks
be reselected. We minimize the impact of two updates by locating
the first update before parasitic data are loaded or SI is enabled.
Since run time is significantly longer, we identify key STA modes
to concentrate on from an SI perspective. When the number of
violations seen in these primary modes is sufficiently reduced,
we can run STA modes for final analysis and fixing.
- Until recently PrimeTime-SI filter variables have been tricky to
determine and, if set too high, can mask out SI effects.
Thankfully, on 2004.06, the defaults have been set so that
hopefully this should not be an issue. PT-SI's configuration
variables allow the designer to optimize the trade-off between
accuracy and performance. Three configuration variables are
particularly important to accuracy and performance. To avoid being
too pessimistic, we set timing_remove_clock_reconvergence_pessimism
to true. Unfortunately, doing this adversely affects tool
performance, so, if your preventative measures have more-or-less
eliminated crosstalk on the clock tree network, one could set this
to false and reap the benefits in terms of performance. Secondly,
we set si_xtalk_reset_critical_path to false (now the default) to
improve accuracy. Thirdly, we believe that the PT-SI variable
si_xtalk_exit_on_max_iteration_count can be set as low as 2 to
avoid increasing already long timing updates. However, it may be
useful, as negative slack is reduced, and the number of PrimeTime
sessions required drops, to increase accuracy by increasing
this variable.
3. Generating Fixes
Crosstalk can be "fixed" by moving the victim net away from major
aggressors, by increasing the drive strength of the victim net driver,
by the insertion of a buffer in the victim net, or by reducing the
strength of aggressor net drivers. We utilize all but the last option
as we felt that could adversely impact non-SI timing. We
automatically analyze all timing violations individually and fixes
are generated based on characteristics of the failing path and the
value of user defined variables.
Our max delay violations are fixed by cell upsizing or wire repelling.
Min delay violations are fixed by cell insertions or wire repelling.
Theoretically, wire repelling alone can fix all crosstalk induced
violations but this approach can be more iterative than desirable,
especially with timing paths through highly congested areas.
- PrimeTime-SI Flow. We use two nested loops to process a
collection of violating paths. The outer loop processes failing
paths, the inner loop processes timing "points". Points are the
key to analyzing timing paths with respect to cross talk. Points
are a PrimeTime collection and an attribute of timing paths. By
querying points, we can determine crosstalk contributions
"x_delta" at each section of a path. Using points, we partition
failing timing paths into driver net-receiver segments and
determine the crosstalk on each segment. Crosstalk depends on
the signal transition which can also be discovered from reading
properties from the timing path point. If the crosstalk on the
segment is found to be less than a user supplied variable
(delta_min), the crosstalk contribution is deemed to be negligible
and the next segment is processed. If the crosstalk delta exceeds
delta_min, then an upsize fix is determined for max delay
violations.
After analyzing each timing path, we compare the ratio of the
total crosstalk contributions along the path divided by the abs
(slack) against a second user-supplied variable (ratio_min) to
determine the ease of obtaining a complete wire fix. Paths with
ratios exceeding ratio_min are considered to be good wire fix
candidates and are added to a collection of paths for Astro
fixing. Paths with ratios below this threshold are fixed by cell
upsizing (max delay) or buffer insertion (min delay). Both
upsizes and buffer insertions are not carried out in real time,
but are written to a write_script file that Design Compiler can
use to generate a new netlist or PrimeTime-SI can use to verify
the fixes actually worked. When all paths have been analyzed a
complete collection of paths for fixing by Astro has been
generated. A Synopsys-provided script generates a wire repeal
script the last stage in the process is to remove redundant lines
from the scheme and write_script files. Nets with crosstalk
delays can generate multiple failing timing paths and therefore
multiple entries in fix files.
- Cell Insertion. We used Delay cell insertion to fix min delay
violations. But cell insertion must be applied with discretion,
or the design changes will result in further design iterations.
In order to reduce this risk, we chose delay cell for its
relatively small size and large delay.
On failed timing paths, we found the total negative slack and
divided by a guard-banded estimate of the delay cell's delay
value. We rounded up this result to find is the number of delay
cells to be added at the path endpoint to remove the violation.
Once the cell insertions are determined, they are then written
to a write_script. Design Compiler or PrimeTime then processes
the write_script to generate a new netlist or check the timing
associated with the fixes.
- Route Based Fixing. Not all crosstalk induced timing violations
are fixed on the first iteration of the Astro wire-repelling
methodology, and we can frequently recover some but not all of
the crosstalk deltas. Sometimes the reduction is insufficient to
fix a violation. To improve the first time success rate of wire
fixing, we use a variable (ratio_min) to determine which violating
paths are to be included in a collection that will be fixed by net
repelling. This collection is passed to a customized version of
Synopsys' create_astro_xtalk_constraints procedure (in 2004.06
this is a built-in command). This procedure is set for crosstalk
delay (not noise), net_isolation, five worst nets and five worst
aggressors. The output from the procedure is a net-isolation
constraints file that's read in by Astro.
- Cell Upsizing. We used upsized driver cells to fix max delay
violations on victim nets. One benefit of upsizing versus cell
insertion is that upsizes aren't likely to disturb routing and
keep the original parasitic file accurate. Routing changes make
the original parasitic file inaccurate, and can also propagate an
entirely new set of timing violations. By avoiding significant
routing changes, we can use original parasitic file with
confidence, and also feel confident of accuracy of the
verification of the upsize fixes. Upsizing the driving cell of
a victim net increases the chances that this victim net could
be a significant aggressor. To fix victim nets without creating
new violations, we tailor the degree of cell upsizing by
selecting the new driver strength based on the size of the
crosstalk delta.
The "get_alternative_lib_cells" command finds alternate driver
cells and Tcl code is used to extract all valid strength values
from the cell names. These strengths are put into an array,
sorted and a pointer set to the current drive strength. The
crosstalk delta found on the victim net is measured against
four user supplied threshold values. Depending upon which
threshold is met, the driver strength is increased by one, two,
three or four increments or to the maximum value, which ever is
closer. Cell upsizing is not always possible for a number of
reasons; the target cell may already be at the maximum strength
or the driving cell (such as ROM, RAM or pad) has a fixed driving
strength. So far, net repelling has been the sole option for
fixing these cases, but it should be relatively straightforward
and desirable to enhance the methodology to include an option for
fixing these by buffer cell insertion.
Here is the procedure that we used:
# FIX_MAX_BY_UPSIZING
# Colin MacDonald/Anis Jarrar, Freescale Semiconductor, July 2004
# Summary: Automatically Determines & Writes Cell Upsizes to a file
# Example of Usage:
# set ups_fid [open Upsize_Test.rpt "w" ]
# fix_max_by_upsizing -Upsize_FID $ups_fid -Target_Cell DUT0/RAM1h \
# -Xtalk_Qnty 0.5 -Incr_by1 0.1 -Incr_by2 0.2 -Incr_by3 0.5 \
# -Incr_by4 0.7
# close $ups_fid
proc fix_max_by_upsizing { args } {
parse_proc_arguments -args $args p_args
if {[info exists p_args(-Upsize_FID)]} {
set ups_fid $p_args(-Upsize_FID)
}
if {[info exists p_args(-Target_Cell)]} {
set tgt_cel $p_args(-Target_Cell)
}
set pth_slk "---"
if {[info exists p_args(-Path_Slack)]} {
set pth_slk $p_args(-Path_Slack)
}
if {[info exists p_args(-Xtalk_Qnty)]} {
set xtk_ctr $p_args(-Xtalk_Qnty)
}
if {[info exists p_args(-Incr_by1)]} {
set inc_1vl $p_args(-Incr_by1)
}
if {[info exists p_args(-Incr_by2)]} {
set inc_2vl $p_args(-Incr_by2)
}
if {[info exists p_args(-Incr_by3)]} {
set inc_3vl $p_args(-Incr_by3)
}
if {[info exists p_args(-Incr_by4)]} {
set inc_4vl $p_args(-Incr_by4)
}
set max_siz_unf false
set tgt_nam [get_attribute [get_cells $tgt_cel ] ref_name]
set tgt_lib_cel [get_lib_cells -of_objects [get_cells $tgt_cel]]
set tgt_brk [string last _ $tgt_nam ]
set tgt_bp1 [expr $tgt_brk + 1]
set tgt_str [string range $tgt_nam $tgt_bp1 end]
set tgt_beg [string range $tgt_nam 0 $tgt_brk ]
if { $tgt_str == "1p5" } { set tgt_str 1.5 }
set uns_str_lst [list $tgt_str]
set tgt_lib \
[get_attribute [get_libs -of_objects $tgt_lib_cel] full_name ]
set alt_clz \
[get_alternative_lib_cells $tgt_cel -libraries $tgt_lib ]
set alt_clz [filter_collection $alt_clz "base_name =~ ${tgt_beg}* "]
if { [sizeof_collection $alt_clz] > 0 } {
foreach_in_collection ic $alt_clz {
set bas_nam [get_attribute $ic base_name ]
set cel_brk [string last _ $bas_nam ]
set cel_beg [string range $bas_nam 0 $cel_brk ]
if { $cel_beg == $tgt_beg } {
set cel_bp1 [expr [string last _ $bas_nam ] + 1 ]
set cel_str [string range $bas_nam $cel_bp1 end ]
set cel_beg [string range $bas_nam 0 $cel_brk ]
# Dont allow 1p5 cells, too little improvement
if { $cel_str != "1p5" } {
set uns_str_lst [lappend uns_str_lst $cel_str ]
}
}
}
set srt_str_lst [lsort -real -increasing $uns_str_lst ]
set srt_str_len [llength $srt_str_lst ]
set tgt_ndx [lsearch $srt_str_lst $tgt_str ]
set ndx_dlt 0
if { $xtk_ctr > $inc_1vl } { set ndx_dlt 1}
if { $xtk_ctr > $inc_2vl } { set ndx_dlt 2}
if { $xtk_ctr > $inc_3vl } { set ndx_dlt 3}
if { $xtk_ctr > $inc_4vl } { set ndx_dlt 4}
set new_tgt_ndx [expr $tgt_ndx + $ndx_dlt]
if { $new_tgt_ndx >= $srt_str_len } {
set new_tgt_ndx [expr $srt_str_len - 1 ]
}
if { ($new_tgt_ndx == $tgt_ndx) && ($xtk_ctr > $inc_1vl) } {
set max_siz_unf true
}
set new_tgt_str [lindex $srt_str_lst $new_tgt_ndx ]
if { $new_tgt_ndx != $tgt_ndx } {
set tgt_string "${tgt_lib}/${tgt_beg}${new_tgt_str}"
puts $ups_fid "size_cell $tgt_cel $tgt_string $pth_slk $xtk_ctr"
}
}
return $max_siz_unf
}
define_proc_attributes fix_max_by_upsizing -info "
Description:
Generates a cell upsize for a driver depending on the xtalk delta
on the receiver and the user supplied thresholds for upsizing. Each
threshold needs to be exceeded for the upsizing to be attempted.
Outputs write_script format command to Upsize_FID. Extra info in
other columns can be filtered out. This procedure relies on all
library cells to be named in the format base_cell_strength e.g.
buf_2, buf_4 etc. This procedure returns a boolean max_siz_unf set
to true if the cell cannot be upsized. Cells cannot be upsized if
already at maximum strength or no stronger versions exist e.g.
RAMs, ROMs, pads
Report File Format:
size_cell cell_instance cell_lib/upsized_cell path_slack xtalk_qnty
Both path_slack and xtalk_qnty (cross-talk delta delay) are the values
supplied as arguments. If optional argument -Path_Slack is not
provided, the default is used
Command Line Usage:
fix_max_by_upsizing " \
-define_args { \
{-Upsize_FID "File handle variable for file holding upszie fixes " \
"ups_fid" string optional} \
{-Target_Cell "Full cell instantiation to be upsized" \
"tgt_cel" string } \
{-Path_Slack "Slack in path containing cell, for reporting only" \
"pth_slk" string optional} \
{-Xtalk_Qnty "Crosstalk delta contribution to net driven by cell" \
"xtk_ctr" string } \
{-Incr_by1 "Crosstalk delay required cause upsize by one" \
"inc_1vl" string } \
{-Incr_by2 "Crosstalk delay required to cause upsize by two" \
"inc_2vl" string } \
{-Incr_by3 "Crosstalk delay required to cause upsize by three" \
"inc_3vl" string } \
{-Incr_by4 "Crosstalk delay required to cause upsize by four" \
"inc_4vl" string }}
"
4. Design Compiler Cell Fixes
In order to modify the netlist so that all our crosstalk design changes are
incorporated, Design Compiler needs to source the design changes and
regenerate a new updated netlist. Since it is not currently possible for
PrimeTime to output a modified netlist, we use two step approach. First,
netlist modifications generated by the PrimeTime crosstalk fixing procedures
are written to a file in write_script format. Second, this file is sourced
by Design Compiler and a proprietary, encrypted procedure from Synopsys is
run to generate the updated netlist. The procedure results in the creation
of new nets to support the buffer insertions. These will not be annotated
until new parasitics are generated.
5. Automated Astro Net Repels
Because Astro and PrimeTime sometimes differ on how nets are referenced,
Astro may not be able to find net references in the net isolation file. To
avoid this problem, we use an alternative format for the net isolation file.
Our net isolation file indirectly references nets based on the nets' driving
pins. If our alternate format is used, the getNetOnInstPin.scm file should
be sourced by Astro.
To perform the net repelling fixes automatically we loaded the net isolation
file into Astro, enabled timing-driven spacing is and performed search and
repair. Depending on the size of the design this took a number of hours to
run. Once complete, we extracted the new parasitic data and fed it back
into PrimeTime-SI for checking. When victim nets were in congested areas,
we looked at the signal's environment and implemented customized fixes that
might be difficult to do automatically.
Astro's slick net editing capabilities -- such as the automatic building of
via stacks -- made cutting tracks and moving segments to other very easy
for use to do. One issue we found is that the net isolation file does not
contain additional information such as the total crosstalk delta on the
victim net or amount of contribution from each aggressor. With that
information, we could decide how many of the victim nets to move and which
of the aggressors to really avoid.
- Colin MacDonald
Freescale Semiconductor Austin, TX
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