( ESNUG 432 Item 5 ) -------------------------------------------- [08/25/04]
From: Jon Stahl <jstahl=user domain=avici spot calm>
Subject: User Needs Help DC Synthesizing & PrimeTime Analyzing Odd Design
Hi John,
We have an arbiter design that we think is elegant and would like to use but
are having trouble figuring out a straightforward way to process it through
Design Compiler synthesis and PrimeTime analysis.
In short, our complete arbiter is composed of arbit elements, each of which
takes bid and control signals. The elements are connected in a 8x8 2-D
torus (mesh with end-around-to-beginning connections). Therefore,
combinational loop paths exist in the form of 8 element rings. However,
these paths will always be broken by external control signals which have
a one-hot encoding.
After some searching and questioning of Synopsys, we still haven't found a
way to constrain control inputs of a design to either one-hot encoding or
some analogous constraint. While this arbiter design may not be common, we
don't believe it to be novel, and are hoping someone may be able to help us
with a better idea how to synthesize and time it than some of the kludgey
ones we have thought up on our own.
- Jon Stahl
Avici Systems N. Billerica, MA
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