( ESNUG 432 Item 1 ) -------------------------------------------- [08/25/04]
Subject: ( SNUG 04 #7 ) Mentor Rep says use the latest MBIST Architect
> MemBIST Architect: does not support RTL insertion correctly. It needs
> to have more knowledge on ASIC design flows and styles to handle this
> correctly. This is always a problem. The gap between EDA and ASIC
> design community becomes larger and larger.
>
> - Xinli Gu of Cisco
From: Jay Jahangiri <jay_jahangiri=user domain=mentor spot calm>
Hi John,
Some of these postings may have been based on older versions of the tool
which did not include many of the recent enhancements.
One of the postings pointed out flow and usability issues with
MBIST Architect. In order to improve the flow and increase productivity,
we recently added a capability to MBIST Architect that inserts BIST
controllers into the netlist automatically. Now users can choose a
top-down or bottom-up implementation flow. The tool will identify the
memories in the design and insert BIST controllers based on the user's
preferred configuration. All customization features of MBIST Architect
have been preserved for this flow so users do not have to compromise on
flexibility.
> MBIST Architect: version 2004.3
>
> MBIST Architect seems to have about 1 weeks worth of learning curve.
> It is possibly the only Mentor DFT product that still needs to be
> improved. The gate counts are still pretty high and we still have a
> very high bug detection rate in it. The QC process for this tool
> needs to be improved because a bug in the MBIST structure means a
> hardware change and is not as easy to fix as a software bug.
>
> - Denzil Fernandes of Texas Instruments
The reason that some of your readers reported higher gate count is that
in some situations the new at-speed feature, which some of our customers
have successfully ran at 1 GHz, does require more gates. The ability to
test memories at-speed has become a requirement for our customers who
need high quality for their nanometer designs so we felt the extra gate
count was acceptable in order to maintain the high test quality. The
BIST controllers generated by MBIST Architect for slow speed operation as
well as some of the at-speed configurations continue to have the low
gate count our customers are used to seeing.
To increase test quality, we've added customization features such as
user-defined algorithms which allows users to program their own test
algorithms that fit the testing requirements of their particular
memories. Since the best-suited BIST algorithms are not always known
prior to silicon, MBIST Architect's on-line algorithm selection allows
users to apply any combination of pre-defined algorithms based on the
failures they're seeing on the tester. Finally, we can now speed up the
BIST simulation process by using short BIST algorithms that verify
correct BIST operation without the need to simulate the algorithm for
every address location.
- Jay Jahangiri
Mentor Graphics Corp. Wilsonville, OR
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