( ESNUG 431 Item 11 ) -------------------------------------------- [07/14/04]
Subject: ( ESNUG 417 #11 ) Another User's First Impressions Of Nassda Hanex
> I saw a demo of Nassda's Hanex at DAC. I haven't used it yet, this
> feedback is only based on the demo that I saw.
>
> - Ken Wong
> Conexant Systems, Inc. San Diego, CA
From: Martin Foltin <mxf=user domain=fc.hp spot calm>
Hi, John,
Below are is my impression of Nassda's Hanex, based on the DAC'03 demo
that I saw, as I have no direct experience using the tool.
Hanex is a transistor level hybrid static/dynamic timing analysis tool.
It combines advantages of fast runtime performance and exhaustive
coverage of static timing analysis (STA) and high accuracy of dynamic
timing analysis (DTA).
Strengths:
1. The concept of concurrent state update. PrimeTime is very limited
in considering the functional & temporal correlations between
multiple inputs of a gate/channel connected stage. The side branch
activation values are usually set to yield only the minimum and the
maximum delays. With concurrent update, the side branch values depend
on true timing arrival windows of these signals. This is accomplished
by propagating concurrently the rising, falling, toggling & uncertain
state windows along with the logical zero and one static logic states
to all inputs of a stage. This approach should:
- Eliminate many false paths, which is a common problem in STA.
- Generate much more realistic timing windows for cross-talk
analysis than PrimeTime.
- Provide correct timing for simultaneously switching signals.
This is not always true for PrimeTime may, for example, give
optimistic delays for simultaneously switching signals in
min-time analysis.
2. The ability to use piece-wise linear signal waveforms at block
inputs, rather than just a linear ramp stimulus. The circuit is
partitioned to stages in such way that the feedback loops, domino
logic, etc. are enclosed in a single stage and simulated with ultra
fast and well-proven HSIM SPICE engine. It considers Miller
capacitance & voltage dependent capacitance. This should give very
high accuracy. The clock propagation is done with fully dynamic
simulation for the highest accuracy. For cross-talk analysis, the
aggressor drivers can be included in the analysis (rather than just
approximated by ideal voltage ramps) for higher accuracy.
Needs Improvement:
Timing model generation for hierarchical timing analysis. Hanex
currently supports black-box timing models. For highest performance
designs relying on level triggered latches and time borrowing, it would
be useful to offer timing models supporting transparency (gray-box or
similar). On the block level, however, Hanex fully supports
transparent latches as well as dynamic (domino) logic and should be
ideal for the highest performance designs. It is unknown to me if
Hanex supports pulse latches. It accepts SPICE netlist in various
flavors of SPICE, Verilog netlist and SPF/DSPF/SPEF for post-layout
parasitic back-annotation.
Bottom Line:
I am not aware of any other commercially available transistor level
timing analysis tool that supports concurrent update, provides
sophisticated cross-talk analysis and takes advantage of a hybrid
static/dynamic approach to the level that Hanex does.
- Martin Foltin
Hewlett Packard Fort Collins, CO
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