( ESNUG 431 Item 8 ) --------------------------------------------- [07/14/04]
Subject: ( ESNUG 430 #5 ) Mapping Xilinx Slices In Those FPGA Benchmarks
> This guy used Xilinx slices as a measure of the quality of the synthesis
> results. Based on the Xilinx seminar I attended recently, I don't
> believe this is a proper metric. In the seminar, the Xilinx AE discussed
> the issue of slice utilization and improvements in their reports
> specifically targeted at getting a better understanding of device
> utilization. They explained that currently, if the device is not
> particularly full, synthesis tools can liberally use slices to give
> maximum flexability when placing and routing the design. The objective
> being to reduce the impact of routing delays.
>
> - Jim Lewis
> SynthWorks VHDL Training Tigard, OR
From: Charlie Anderson <c.anderson=user domain=microcontrol spot calm>
Hi John,
In regards to ESNUG 430 #5, there is a Xilinx tool switch to fit only
slices necessary (i.e. at the expense of net delay). There is a selection
under the MAP option for CLB pack factor percentage (Xilinx ISE flow).
The default value is set to 100%. If you change this to say 1%, the tool
will minimize the slices in your design. We've used this strategy to
compare the MAP report files for headroom in our designs. Then you have
a better feel for the design and spare resources. There is a similar
switch for the XST Synthesis tool, but we found this less useful in
predicting size.
- Charlie Anderson
Micro Control Company Minneapolis, MN
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