( ESNUG 425 Item 9 ) -------------------------------------------- [03/24/04]
Subject: ( ESNUG 423 #14 ) Aart on Assertion Languages
> There is a lot of confusion about different assertion languages and libs
> at the moment:
>
> PSL: Property Specification Language
> OVL: Open Verification Library (Verilog modules)
> OVA: Open Vera Language
> SVA: System Verilog Assertions
> SVL: System Verilog assertion Library (SVA version of OVL)
>
> Q: Is the assertion language war a red herring? Assertions are often
> easy to write but the real problem is that EDA tools (and engineers)
> struggle to formally prove them!
Accellera has defined System Verilog as the language standard that unifies
design and verification, including assertions. The inclusion of assertions
as part of a design and verification language in System Verilog provides
the basis for widespread adoption of Design for Verification techniques.
We have successfully deployed assertion solutions in our customer base
for over two years, with success in both dynamic (simulation based) and
static (formal property) verification environments.
It is our expectation/hope that Accellera is aligning PSL with SVA so
that an assertion language war will be averted.
Assertion libraries are important to ease the adoption of assertion-based
verification, and that is why we have provided a library of more than
50 assertion IP components with VCS for over a year now.
- Aart de Geus, CEO
Synopsys, Inc. Mountain View, CA
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