( ESNUG 425 Item 8 ) -------------------------------------------- [03/24/04]
Subject: ( ESNUG 423 #12 ) Aart on 90 nm Design Issues
> Who do the CEOs think will actually be doing 90nm designs? Given the
> monster designs needing verification and implementation tricks/tools
> that don't yet exist, 90 nm is out of reach for majority of silicon
> builders. I can think of Intel, IBM, but the list gets real short real
> fast. So, who do the EDA heads think will be actually targetting 90nm
> and why and when?
The primary motivators to move to 90nm today are high speed and integration
of many functions on a single die. The first customers we saw moving to
90nm were in the wireless and microprocessor sectors, followed by
high-speed networking and graphics processor companies.
Once the yields are up, we expect to see more companies move to 90nm for
the cost advantages as well.
> I was at DATE-04 last week and the issue of how much it costs to design
> in a techno like 90 nm was not adequately answered. Costs range
> $20M-$50M for a single chip design were mentioned. Solutions like IP
> reuse, platform design and various high level design tools were talked
> about, but the consequent saving in design cost wasn't. My question is:
> If you design in 90nm and use all the suggested options to reduce design
> cost like IP reuse, platform design and high level design tools, what
> will be the saving in design cost? What will be the associated added
> cost to buy in the IP, platform, tools etc?
The International Technology Roadmap for Semiconductors for 2003 (ITRS)
has warned:
"The main message in 2003 remains -- Cost [of design] is the
greatest threat to continuation of the semiconductor roadmap."
The roadmap predicts a 5X increase in design productivity between now
and 2007. Most of that productivity comes from reuse of IP blocks
bigger than 1 million gates. The 65nm chip in 2007 that is on the
roadmap will have 31M gates of reused logic, a similar amount of new
logic, and over 30 megabytes of memory.
Looking at these numbers clarifies why Synopsys is putting so much
emphasis on assembling a very high-quality IP portfolio. Not only will
it positively impact design productivity as users move to the next level
of abstraction, but it will also reduce risk when mapping to the new
silicon technologies. As we move to smaller geometries, our IP will
become more and more tuned to specific silicon to avoid signal integrity
issues, deal with leakage currents, be optimized for yield, etc.
There will still be plenty of complex design challenges for IP users,
because the chip assembly and the design of the dedicated logic will be
just as taxing technically as any of the sub-blocks. Increasingly we
see our users teaming up with a preferred EDA vendor to reduce both risk
AND cost. Although it is always possible to amend one vendor's flow
with some promising individual point tools from another vendor, we
observe more and more that the benefits of tools that work well together
typically outshine glued-together alternatives. There are many reasons
for this, including better correlation due to timing and signal
integrity understanding and the advantages of using the same constraints
and scripts, to name a couple.
I think that one reason you didn't hear a definite answer about cost at
DATE '04 is that it is difficult to assess costs across a broad spectrum
of designs. Right now, I believe that design costs have reached a
plateau and will not change markedly in the near future.
However, it is clear that the highest cost of all is "risk cost." A
single additional spin not only blows out the budget, but it can also
kill the schedule and jeopardize the most profitable market phase of a
product. To minimize these risks, more and more of our customers use
small engagements by our services groups on their chips to help "steer
their ship" during critical timing closure, test, and routing phases,
where we may be able to bring some very specialized resources and
experience to help them.
In short, the relationship between design groups and EDA partners must
get closer for designs to succeed. We are both interested in IC design
remaining viable for a broad set of applications. At Synopsys we are
committed to help reign in the growth of design costs through innovation
and integration.
> The foundry and fab bosses tell us that at 90nm and 65nm the big problem
> is sub-threshold leakage. This partially or completely negates the
> traditional benefits of the shrink. So what are EDA firms doing to cope
> with this unknown factor in their front end and back end tools?
Leakage power becomes a big problem at the smaller geometries, necessitating
new design techniques and EDA tool support. One common way to reduce
leakage current is to use high threshold voltage devices, which are slower
but consume less power.
Power Compiler automatically trades off between timing and leakage power
by selecting high Vt devices for non-critical paths, while selecting
faster, higher-leakage, low-Vt devices on critical paths in order to
meet timing constraints. In addition, Synopsys is developing support
for Power Gating, an optimization technique using a new device that
operates at high speeds when active, but consumes almost no power when
shut down by the circuit.
Another technique that has been used successfully is to change both
voltage and frequency (dynamically) as a function of the computational
needs of the moment. National Semiconductor, ARM, Artisan, and Synopsys
have collaborated on some very interesting capabilities in that
direction.
In addition to addressing leakage through EDA tools, our EDA solution
will also address this critical issue through the MoSys 1T-SRAM IP. The
1T-SRAM is actually a dynamic bit cell at its heart (one transistor and
capacitor) with no connections across the power rails. So, unlike
traditional 6T-SRAM architectures, the MoSys 1T-STAM memory is really
not faced with the same leakage issues as 6T cells. MoSys has measured
the leakage of their 1T-SRAM memories in "retentive standby mode" to be
about 25% of comparably sized 6T memories.
> With the vast numbers of transistors available at 90nm and beyond, will
> the EDA industry slip behind or be able to keep up with the silicon?
The phenomenon of the "design gap" is not new at 90nm. It has been a
consistent challenge for EDA tools to keep up with the silicon
opportunity. Historically, we have witnessed multiple waves of
innovation, such as automatic place & route, synthesis, static
verification, and physical synthesis, all of which have enabled EDA to
keep pace. Each wave of productivity is invariably tied to moving to a
higher level of abstraction for large portions of the design-from
rectangles to transistors, to gates, to small macros, to cores, etc.
I recently sat next to Gordon Moore at an event, and I asked him whether
Moore's law was still alive. He said that he believed it was not only
alive, but that it actually may be accelerating! EDA's job is to keep
design on pace with Moore's law; and through our tools and methodology,
we believe we are doing exactly that.
For 90 nm and beyond, we are innovating in areas like power management,
design for yield, on-chip variation, test diagnosis, and signal
integrity in order to meet technical demands.
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