( ESNUG 425 Item 7 ) -------------------------------------------- [03/24/04]
Subject: ( ESNUG 423 #10 ) Aart on SystemC, System Verilog, Vera, VCS
> Why Aart went SystemC, SystemC, ooops System Verilog?
SystemC is not going away. Synopsys created SystemC, and it has been
successful in the system modeling space; but it was never intended to be
an HDL or verification language. Actually, we have increased our
investment in SystemC integration in the verification flow, with the
integration of System Studio with RTL verification (Vera and VCS), as
well as SystemC integration with VCS.
SystemC and SystemVerilog are complementary languages, each optimized to
address a specific need in SoC design and verification. SystemC is for
C and C++ centric users who are working at a system architectural level
and need a language that is closer to the software world, as well as a
language for modeling IP at the transaction level for system-level
architecture exploration. System Verilog is used by RTL design and
verification teams. These teams are concerned about absolute bit-by-bit
accuracy, very fast run times, and the ability to describe a rapidly
growing number of assertions and properties that help reduce the state
space that has to be verified.
Our focus at Synopsys is the smooth integration of SystemC models in a
System Verilog design and verification environment to provide the
benefits of both languages to our customers.
> Are you worried that by pushing System Verilog so early, you might be
> eating into sales of Vera/VCS?
On the contrary! We are seeing Vera and VCS business grow because of
enhanced testbench technologies (constraint solvers) in Vera, our support
for System Verilog, and the built-in testbench and assertion technologies
in VCS.
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