( ESNUG 425 Item 3 ) -------------------------------------------- [03/24/04]
Subject: ( ESNUG 423 #4 ) Aart on FPGAs & Structured ASICs
> Do you think that Structured ASIC is a bunch of hype, or will it
> displace current FPGA and CBIC solution (to include low cost Standard
> Cell in older process generations, e.g. 0.25um, 0.18um)?
>
> How will the adoption of Structured ASICs affect the EDA communities'
> revenue given that they are supposedly easier to design and require
> fewer physical design and verification tools (e.g. P&R tools) because
> master slices can now support dozens of designs without new placement,
> meaning fewer tools necessary?
Structured ASICs in general provide an interesting value proposition. The
jury is still out as to whether the business model will work and the market
will take off, since many approaches appear too focused on small
niche markets.
One of the most promising pathways is to use our tool set to do FPGA-based
design that can easily be mapped into an ASIC if the production volume
warrants it. Synopsys tools are being used today in the design of FPGAs,
structured ASICs, and complex SoCs. The very fact that our toolset can be
seamlessly used from one implementation technology to another gives users
a higher degree of flexibility.
As far as the impact on EDA revenue, structured ASICs should have no impact
on license usage, so we don't anticipate an effect on revenue.
> I'd like to know how each vendor sees the "rise of FPGAs" hitting them.
> More design-starts are going to FPGAs, due to their increasing
> capabilities and obvious time-to-market advantages. The FPGA EDA tool
> business sucks (in comparison to the ASIC EDA tool business, at least),
> how do these guys plan to stay in business?
Perfect timing for this question, since we just introduced DC-FPGA at our
San Jose SNUG conference. We see the complexity of FPGAs growing rapidly
and, with it, both the design challenges and the implementation
opportunities requiring "ASIC-strength" tools and flows.
For limited volume, high-end FPGAs are a good implementation vehicle,
competing well with low-end ASICs. By providing a set of tools and a
design flow that lets designers map easily into either implementation,
we give our users higher technical and economic returns on their tool
investment with us.
Meanwhile, design starts for ASICs are down, but the size of the designs
has gone up tremendously, fueling growth in the EDA tool market.
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