( ESNUG 423 Item 10 ) ------------------------------------------- [02/26/04]
Subject: SystemC, System Verilog, Verisity "e", and Brett Questions
Brett - When will system design be real? what will take to make system
design real?
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My question is about the future of high-level verification languages. My
understanding is that the three major languages (SystemVerilog, SystemC, and
E) are all pursuing separate IEEE standards. Also, SystemVerilog is under
development by two separate organizations (Accellera and IEEE) that don't
get along.
My main question (as an EDA user) is: "Who really cares about these
committees and their standards anyway?"
First, if IEEE has three "standards" for solving the same problem, what does
the word "standard" even mean? Second, does anyone really believe that
committees are going to produce a good definition of SystemVerilog? Look
at Verilog, C/C++, Perl and all the other languages we use. They were
developed by a small group of engineers and weren't standardized until after
they achieved worldwide domination.
I'd like one of these CEOs to admit that all this focus on standardizing is:
1. Premature
2. Ineffective
3. A big waste of time.
Thanks!
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Synopsys sent letters this week to their customers notifying them that the
Behavioral Compiler and CoCentric SystemC Compiler products are officially
being end-of-life'd. With Synopsys continuing to back away from SystemC,
does SystemC stand a chance? And If Synopsys doesn't think they can make
money in SystemC behavioral synthesis, how can Forte expect to?
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I would ask Mr. Cline, what have you done for any one lately other than
Tensilica. How is life without J. Segrunati? How long will the company
survive given that its riding the dying SystemC wave?
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How about:
"Hey Brett, it looks like Ray's water is getting a little low, would you
mind refilling it? And why don't you fetch some doughnuts while you're
at it."
Its all in good fun, I like Brett.
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4) HDL language support (to All vendors)
Will verilog eventually lose to System Verilog? How are EDA companies
assessing support for different HDL's in terms of SystemC, SystemVerilog
or for that matter, Verilog itself? What's the market requirement in
terms of requests pouring in for the support of SystemC/System Verilog?
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Is there room for all of SystemC, System Verilog, Verilog and e, or
should there just be System Verilog?
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4. Ask all the CEOs will they be supporting SystemC? Is this a real working
language or a fantasy?
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Brett, Forte has decided to focus on C based synthesis by end-of-lifeing
Quickbench. Why focus on a market that has limited growth potential (DSPs)
especially when designers have expressed little interest in the technology
as a whole? BehavorialCompiler failed for a reason.
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