( ESNUG 423 Item 4 ) -------------------------------------------- [02/26/04]
Subject: Synplicity, FPGAs, Structured ASIC, Bernie Types Of Questions
1. Do you think that Structured ASIC is a bunch of hype, or will it
displace current FPGA and CBIC solution (to include low cost Standard
Cell in older process generations, e.g. 0.25um, 0.18um)?
2. How will the adoption of Structured ASICs affect the EDA
communities' revenue given that they are supposedly easier to design and
require fewer physical design and verification tools (e.g. P&R tools)
because master slices can now support dozens of designs without new
placement, meaning fewer tools necessary?
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Bernie, how will Synplicity's partnership with LSI for RapidChip help it
penetrate the ASIC EDA market?
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"How come Synplicity can be a "successful" company in FPGA EDA, but
everyone else fails" - Gives Bernie something to talk about...
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Do we need to change the perception that FPGA tools should cost much less
than ASIC tools used on designs of similar size? Will FPGA technology be
limited by the lack of high-end and analysis tools (timing, signal
integrity, etc) if we don't?
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2. What's the best way to keep my FPGA design from being copied? (We
see bootleg versions of hardware coming back as RMA gear!)
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Any thoughts about implementing a more FPGA friendly pricing model? Would
the increased sales volume from FPGA designers offset the lower prices?
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I also want a gauge on design starts and why EDA tool vendors aren't more
aggressive in the FPGA markets.
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How can EDA survive as ASIC's are replaced by big, intelligent FPGA's?
Who needs all those layout tools when an FPGA will have a million gates,
a few megabytes of RAM, and a processor core? Verification will still
be important, but may still decline.
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1. The fact is that there are less and less cell-based ASIC design starts
year over year. The costs involved in completing a cell-based ASIC project
in 90nm and below are prohibitive for most companies to be able to fund.
Less cell-based ASIC projects mean less EDA revenue unless the toolset costs
increase while design projects decrease. What are Cadence, Magma, and Mentor
Graphics doing to lower the total EDA costs to complete a 90nm cell-based
ASIC design front to back?
2. What strategy is in place from these 5 companies to drive up the number
of design starts?
3. Cadence, Mentor Graphics, Forte, and Magma seem visibly absent from the
platform ASIC design movement or even a majority of FPGA designs being done
today. What are these four companies doing to specifically address this
market space and the FPGA space?
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Questions to Bernie, Rajeev:
Synplicity makes most of its revenue from FPGA Synthesis. Magma has built a
pretty big size group working on FPGA (and Structured ASIC) Synthesis.
However FPGA Synthesis looks more and more like a commodity. It's dirt cheap
compared to ASIC tools. It's now free from Xilinx and Altera (with pretty
good quality of results).
So the questions are: how does Synplicity plan to survive? do they bet
everything on being the first one to be able to dethrone Design Compiler for
ASIC?
And: Why is Magma spending money is a commodity market (declining in term of
$ value).
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2) What is it going to take for Synplicity to take a bigger bite out of
Synopsys?
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I'd like to know how each vendor sees the "rise of FPGAs" hitting them.
More design-starts are going to FPGAs, due to their increasing capabilities
and obvious time-to-market advantages. The FPGA EDA tool business sucks
(in comparison to the ASIC EDA tool business, at least), how do these
guys plan to stay in business?
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There is lots of talk about CAD Vendors not moving into the FPGA market
despite the obvious growth in design starts in this area. Why are the EDA
Vendors unable to provide tools with sufficient ROI to justify their use by
the FPGA Designers? Is there no way to differentiate the CAD vendor tools
from the FPGA vendor tools? If the FPGA Vendor tools are of such high
quality, what is to prevent them from migrating these same tools into the
ASIC marketplace (with extremely competitive pricing)?
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1. A "selling point" of Platform ASICs and Structured ASICs, in addition
to accelerated design times, is lower NRE compared to traditional
ASICs. What are the EDA vendors doing with respect to design tools for
these types of application-adaptable ICs that contributes to lowering
design cost?
2. Do you see a market somewhere down the road for merchant integrated
design tools for embedded arrays (FPGA-like array blocks in cell-based
designs)?
- Jim Lipman
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