( ESNUG 423 Item 1 ) -------------------------------------------- [02/26/04]
Subject: Questions Primarily For Aart
I would be more interested in the story behind why Synopsys is not
represented in this panel.
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I have an edgy question for you. Why is Aart not participating?
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Why would Synopsys pay an egregious amount of money for embedded SRAM
IP? - Wally/Ray should eat this up..
Isn't the IP business EVEN WORSE than the EDA business (if that is
possible)?
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Synopsys, that is missing in your panel discussion, just acquired Mosys,
an IP company.
I'm curious to hear whether these guys think that EDA is reaching a dead
end and they need to spread out into other markets in order to be successful
or whether this is just to secure their market.
CDN and MENT also own big IP libraries. Do they focus more on IP as well
although they were not able to show big success with IP so far?
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My questions for Aart:
1/ Why he went SystemC, SystemC, ooops SystemVerilog?
2/ Has he been infected by the aquisition bug? Avant!,
inSilicon, MoSys etc? Does Synopsys still do internal
development.
3/ What justifies paying $430m for a company with a revenue
stream of around $16m (MoSys)?
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Where's Aart?
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Aart - System Verilog or SystemC. Seems like people do like to model
systems in C, what's going to happen?
- what will take to make system design real?
- SNPS continues to move to the IP space -- "hard IP" now (high
priced MoSys acquisition - now memories are not SOFT IP). Will that
distract from the tools?
- You got HSPICE and ADA, is there more to the analog story at
your shop?
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Synopsys has recently purchased Mosys, and Magma acquired Silicon Metrics.
They and Cadence all distribute TSMC libraries. Is the EDA business
merging with the library IP business?
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I am an equity analyst at B. Riley & Co. My coverage universe includes the
SIP companies (MIPS, ARTI, VIRL, MOSY, ARMHY & CEVA). Given the recent
acquisition of MOSY and Accelerant by SNPS, I want to know why SNPS is
getting back into the business of selling SIP after selling its physical
libraries business to ARTI just two years ago.
Also, I want to know if other EDA tool vendors are interested in getting
back into the IP business. Likely, nobody will answer this question
honestly because nobody wants to show their cards, but it's worth asking.
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Where's Aart?
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2. Ask about a System Verilog update.
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Why isn't Synopsys in the room?
I can design an FPGA with a 1000$ tool suite. I can do a Structured ASIC
for a similar amount (with Altera, for instance). Now what is your
business model again? And if Synopsys does not seem to be able to grow,
why do you think you can?
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Since System Verilog is not sanitized by IEEE, is it truly a standard and
what are the plans to standardize it?
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Consolidation in the IP area is heating up. The recent acquisitions by
Synopsys are examples. Will EDA vendors finally legitimize the IP
industry? That is, will they sell and support IP that is guaranteed to
work in silicon? At present, no one seems willing to guarantee anything.
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What the f___ was Aart thinking paying a 93% premium and 21 times revenues
for Mosys?
Oh, Aart isn't on the panel, never mind :-)
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SNPS is buying a networking company for its SERDES and other IP. Is it
not competing with its own customers now? Reminds me of Cadence's foray
into services ten years ago when you asked Costello why he thought
competing with his customers was a good idea. We all know it turned
out to be a disaster.
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Strange that Art is missing from the forum.
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Memory Design has been typically very different compared to the ASIC design
flow. With the exception of Mentor which once had Memory Builder, none of
the big EDA vendors have actively marketed a tool that aims at addressing
the issues of memory designers. Since this is the one of the fastest growing
market segment for CE, handhelds and portable, are the big vendors planning
to address this market segment. Is Synopsys's acquisition of Monolithic
Systems (a Memory IP provider) a step in that direction?
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Here is a question: "Is Aart's absence from the panel a sign that Synopsys
is in decline?" (Or that Synopsys thinks they are so important that they
can skip the panel?)
More seriously: "Given the shift from ASIC to FPGA design starts, how will
your company demonstrate that your tools are worth the extra cost over FPGA
vendor tools?" Presumably targeted at the first three on the panel. (One
possible answer is to target high level HW/SW co-design, which isn't offered
by FPGA vendors, and is somewhat independent of the HW implementation).
Do you believe that you can outsource most of your phone support to
India/China? (My own belief is increasingly yes. One of my former students
is in Magma's Bangalore office, and most of the staff there are FAEs
supporting local users. So clearly they can hire and train competent people
who can communicate well in English. The only real question is whether they
can do it at a cost significantly lower than the U.S., and whether they can
find enough suitable engineers to hire.)
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Looking at the list, I'm wondering why Synopsys isn't participating....??!!
I think they're still a major EDA company. ;)
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Given that Synopsys seem intent on scaling their potential revenue and value
through acquisition and supply of all types of IP (recent Mosys acquissition
highlights this). Where will it stop? Is it a good play? And if so, what
will Cadence and Mentors reaction be to it?
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This one for Synopsys.
Are you worried that by pushing SystemVerilog so early, you might be
eating into sales of Vera/VCS?
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Aren't we missing someone from this list? The big S?
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When will tools fully support SystemVerilog?
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