( ESNUG 419 Item 6 ) -------------------------------------------- [10/08/03]
From: Jay Pragasam <jlk=user domain=brecis got calm>
Subject: Are Any Users Actually Thinking Of Using System Verilog Out There?
Hi John,
Recently I've been hearing discussions about System Verilog and the push
by Synopsys for users to evaluate it. Though there is not a complete
System Verilog toolset and no tapeout of a chip with System Verilog yet,
there are forecasts that such a flow would be available, sometime mid
next year.
Are there any users out there who are seriously contemplating about
switching to System Verilog? I see that there are advantages at the
coding level in terms of design and verification, but does anyone think
that System Verilog will take off and become mainstream anytime in the
near future. Also I talked to some of Synopsys' competitors whose tools
we have embedded in our design methodology and none of them seem to have
support for System Verilog as a priority.
- Jay Pragasam
Brecis Communications San Jose, CA
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