( ESNUG 416 Item 9 ) -------------------------------------------- [07/30/03]
From: Volker Lueck <volker.lueck=user domain=tesat.de>
Subject: Prover eCheck Was The Best Equivalence Checker For Little Money
Hi John,
This Spring we did an evaluation on equivalence checking tools to find out
what fits best to our requirements, which were
- support for rather small Actel FPGAs
- support for space qualified ASIC technologies
- support for Synplify and Synopsys synthesis tools
- support for rather unusual VHDL constructs as "complex" generics,
unconstrained ports, etc.
- adequate costs in comparison to synthesis cost.
We checked:
- Verplex LEC.3.5.2.a
- Mentor FormalPro v4-4_3-8
- Synopsys Formality 2003.06-FM-Beta
- Prover eCheck 2.1.4a
and found Verplex to show the best performance, Mentor to have the largest
VHDL-constructs support, Synopsys to suffer from good VHDL support and
Prover to show the lowest prices at acceptable performance. No tool was
"best in all categories", all tools would have been usable -- some with
restrictions -- for our designs within our design environment.
As runtime or memory allocation are not critical for our kind of designs,
we decided to purchase Provers eCheck, which showed the best
performance/costs relationship, short turnaround times for solving tool
problems and gave us possibilities to influence the modifications of the
tool to come as close as possible to our needs.
Of course we saw the rather poor mapping algorithms, the VHDL library
support to be enhanced, some VHDL constructs to be added to the
functionality, the debugging to be enhanced by graphical features and
crossprobing and the potential risk when investing into a rather small and
new (at least in this business area) company. But only when giving new
companies a chance, competition takes place and improves the performance
of all competitors.
Our requirements for space applications are rather unusual, so for other
requirements a different decision could make sense.
- Volker Lueck
Tesat-Spacecom GmbH Backnang, Germany
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