( ESNUG 413 Item 6 ) -------------------------------------------- [05/29/03]
Subject: ( ESNUG 408 #3 ) Tharas Follow-up To User Reviews Of 2 Months Ago
> 1. During our use it was hard to use the Hammer for waveform debug for 2
> reasons:
>
> A. Our design just fit into the Hammer and enabling waveform dumping
> would not allow the design to completely fit.
From: Rahm Shastry <rahm=user domain=tharas spot calm>
Hi, John,
The max capacity for one Hammer box is 32 Million Gates. Multiple Hammers
(up to 4) may be combined for verification of extremely large systems.
> B. There was a pretty severe performance hit when dumping waveforms
> (VCS also has this hit but by a smaller factor).
Hammer has hardware support for waveform dumping. For a 5+ Million gate
designs, while dumping 100% of signals, we see a degradation of 2X on
Hammer, while the same for a s/w simulator is around 5X.
> 2. Acceleration varies depending on the design and on the test bench
> architecture. It may be difficult to estimate the acceleration without
> actually trying the device.
Achievable acceleration is an inverse function of testbench activity. A
quick profile during s/w simulation run can help determine max acceleration.
> 1) Now that I can run VCS 6.2 on Linux boxes and I find 2-3x performance
> improvement on 2.4 GHz Dell Linux Servers over the 900 MHz Solaris
> machine, the price of Hammer, as long as it is connected to Sun
> Solaris, does not justify its peformance over Linux machines. Their
> price will be more justified, if I am able to connect Hammer to a
> Linux machine and run my simulation. Tharas is working on this now.
Tharas has been supporting Linux workstation since early 2002.
> Concern: Being a startup, how long will they keep on providing excellent
> customer service to us?
Thanks for the kind words! A happy & productive customer is key to Tharas'
continued success.
> 2. What are its weaknesses?
>
> - Reliance of proprietary ASIC parallel processors. The advantage of
> Hammer's sim throughput is diminishing as Sun or Linux workstation's
> computing power keep on advancing. Our concern is if Tharas can keep
> up the pace.
Processor memory bandwidth is a key measure of a s/w simulator performance.
Hammer architecture offers a sustained memory bandwidth of two orders of
magnitude GREATER than the fastest general purpose workstation available
today -- and to boot, you will never *ever* have a cache miss in Hammer. We
believe this is always true for the foreseable future.
> - Hammer seems to have more compiler switches than I would prefer. In
> my memory, we had to turn on one switch otherwise Hammer can not
> simulate correctly.
It's akin to what you experience using DC - simplicity vs. flexibility. Our
2003 focus is to further "ease of use".
> - Before the purchase, we only used a small set of test patterns to
> check Hammer's performance and we gave Tharas a performance goal.
> Tharas assigned 1 full time engineer, we assign a half time engineer.
> After they met the initial performance goal and we agreed to purchase
> Hammer, we discovered that Tharas may have "optimized out", through a
> compiler switch, part of RTL which aren't exercised by these patterns.
> So the performance data before the purchase decision was misleading.
Hammer has several optimization features that are specific to a certain
class of designs. It is possible in this situation that one of those
features may have been rendered ineffective.
- Rahm Shastry
Tharas Systems, Inc. Santa Clara, CA
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