( ESNUG 413 Item 3 ) -------------------------------------------- [05/29/03]

Subject: ( ESNUG 407 #13 ) Power Rings Using Cadence First Encounter Ultra

> Notching power rings: with the old tools (CDN DP) we were using, putting
> down a rectangular power ring around a core was easy; getting the ring
> to have notches around cells in the corner like PLLs took a great deal
> of hand work.  Eventually, we wrote a script to drive SE sroute to do
> this, but it took awhile to get it written right, and it must be rewritten
> for each new chip.  Now I see CDN FE Ultra can do this automatically if
> the user selects to "exclude selected blocks" when routing the ring.  Or
> at least Cadence says it can.  Can it?
>
>     - Mark Wroblewski
>       ex-Cirrus and looking                      Lafayette, CO


From: Steve Cline <scline=user domain=cadence spot calm>

Hi, John,

Here's how you would do the tasks mentioned in ESNUG 407 #13 concerning
notching power rings in First Encounter Ultra:

There are multiple ways to complete this task in Encounter.  If the Macro is
rectilinear, the tool can create rectilinear rings around such instances. 
Encounter command "addRing" expects the user to select the block/macro for
which the power rings needed to be drawn.  The user could select multiple
blocks if he/she wants to.

 a. Example script for a rectilinear ring around rectilinear block

    selectInst blockA
    addRing -spacing_bottom 10 -width_left 8 -width_bottom 8
            -width_top 8 -spacing_top 10 -layer_bottom metal1
            -stacked_via_top_layer metal5 -width_right 8
            -around selected -jog_distance 5.5 -offset_bottom 5.5
            -layer_top metal1 -threshold 5.5 -offset_left 5.5
            -spacing_right 10 -spacing_left 10 -type block_rings
            -offset_right 5.5 -offset_top 5.5 -layer_right metal2
            -nets {VSS VDD} -stacked_via_bottom_layer metal1
            -layer_left metal2

    If the topology can not be gleaned from the abstract model, the user
    can specify coordinates for the router to complete the power topology
    desired.  The ring could encompass multiple blocks (within the co-
    ordinates).  The co-ordinate of the first point and the last point 
    should be aligned in the vertical or horizontal direction.

 b. Example script for a Rectilinear ring by specifying coordinates

    addRing -spacing_bottom 10 -width_left 8 -width_bottom 8
            -width_top 8 -spacing_top 10 -layer_bottom metal1
            -stacked_via_top_layer metal5 -width_right 8
            -user_defined_region {3565 20750 11240 20750 11730
             22840 13390 22840 13390 38780 3565 38780}
            -around user_defined -jog_distance 5.5 -offset_bottom 5.5
            -layer_top metal1 -threshold 5.5 -offset_left 5.5
            -spacing_right 10 -spacing_left 10 -type block_rings
            -offset_right 5.5 -offset_top 5.5 -layer_right metal2
            -nets {VSS VDD} -stacked_via_bottom_layer metal1
            -layer_left metal2

    If you wish, you can have the Encounter complete the ring around the 
    core, stopping at the ring around the macro.  Encounter command 
    "addRing" can contour the power rings around irregular objects in the 
    pad ring, to generate a desired core ring automatically.  It can handle
    irregular IOs (i.e. IOs that are sticking out) and comes with a rich
    set of options.

    Example script for a Contouring around I/O boundary

    addRing -spacing_bottom 10 -width_left 8 -width_bottom 8
            -width_top 8 -spacing_top 10 -layer_bottom metal1
            -stacked_via_top_layer metal5 -width_right 8
            -around core -jog_distance 5.5 -offset_bottom 5.5
            -layer_top metal1 -threshold 5.5 -offset_left 5.5
            -spacing_right 10 -spacing_left 10 -offset_right 5.5
            -offset_top 5.5 -layer_right metal2 -nets {VSS VDD}
            -follow io -stacked_via_bottom_layer metal1
            -layer_left metal2


> Multiple layers on rings: to reduce the area required for supply rings,
> we used multiple layers.  We also intermingled the nodes in these ring
> stacks, so for example the outer of two rings would be stacked as VDD,
> GND, VDD on 3 of 5 routing layers, and the inner of the two rings would
> be stacked as GND, VDD, GND on some other 3 of 5 routing layers.  Strips
> across the middle on two layers vertically and one layer horizontally
> would tie everything together and deliver the supplies to the row metal.
> We were able to work this by hand, but the old tools (CDN DP, SE Sroute
> in "automatic" usage scenarios) couldn't cope.  Does FE Ultra do any of
> this effectively?
>
>     - Mark Wroblewski
>       ex-Cirrus and looking                      Lafayette, CO


You can specify planar rings, intermingled rings, overlapping rings, etc.

You can even tell the tool which stop points you want (complete to last
target or first target, etc.) for completing the stripe connections to the
rings.  Encounter command "addStripe" has the "extend_to_design_boundary",
"extend_to_first_padring" and "extend_to_area_boundary" options to
accomplish the above variations.  Other options to the command lend
flexibility in the methodology chosen by  the user.

Example script to specify stop points for stripes

 a. Stop stripes at design boundary and create pins

    addStripe -extend_to design_boundary -set_to_set_distance 100
              -stacked_via_top_layer metal5 -spacing 10
              -merge_stripes_value 5.5 -layer metal2 -width 8
              -switch_layer_for_padcorering 1 -nets {VSS VDD}
              -stacked_via_bottom_layer metal1

 b. Stop stripes at first pad ring or pad pin

    addStripe -extend_to first_padring -set_to_set_distance 100
              -stacked_via_top_layer metal5 -spacing 10
              -merge_stripes_value 5.5 -layer metal2 -width 8
              -switch_layer_for_padcorering 1 -nets {VSS VDD}
              -stacked_via_bottom_layer metal1

 c. Stop stripes at the selected area

    addStripe -extend_to area_boundary -set_to_set_distance 100
              -stacked_via_top_layer metal5 -spacing 10
              -merge_stripes_value 5.5 -layer metal2 -width 8
              -area {5869.092 19961.153 9536.248 17725.561}
              -switch_layer_for_padcorering 1 -nets {VSS VDD}
              -stacked_via_bottom_layer metal1


> Power supply design and analysis: Our old way of design and analysis
> for the power supply metal was an MS Excel spreadsheet.  What I really
> was looking for was a tool that studied the placed netlist and helped me
> beef up or trim down the power supply grid.  FE claims to do this.
> What's the truth?  And what kind of clock trees does it assume?  Zero
> skew?  Useful skew?  Or does it use a netlist with clock trees inserted?
>
>     - Mark Wroblewski
>       ex-Cirrus and looking                      Lafayette, CO


You can use VCD files for the activity information and generate power 
dissipation numbers.  Most back-end guys won't have those handy.  So you 
can set typical clock frequency, and percentage toggle on the nets to 
"prototype" the switching.  It is not as accurate as detailed analysis, 
but when you are trying to get "in the ballpark" on sizes, it works. 

Example command to invoke power analysis with VCD files:

      updatePower -pad <PadFileName> -vcd <VCDFileName> -start <time>
                  -end <time> <netName> 

The PadFileName is an ASCII file that gives positions of DC sources; it's
automatically generated by Encounter.

Example command to invoke PA without VCD:

      updatePower -pad <PadFileName> -toggleFile <ToggleFileName>
                  -postCTS <netName>

The ToggleFileName is a User specified ASCII file to define different
toggle rates for each clock domain.

VoltageStorm, IR drop analysis tool is loosely integrated in the latest
release of Encounter.  Designers can perform a more detailed IR drop 
analysis using VoltageStorm. 

Example command to invoke VoltageStorm PA:

      runVStorm -net <netName> -voltLimit <value> -libs <VSPGViewDirNames>
                -powerFile <PowerFileName> -ppFile <PadFileName>
                -analyzeIR 1 

VSPGViewDirNames is the VoltageStorm power grid view libraries.  This is
automatically generated by Encounter by calling libgen executable. 

PowerFileName is the instance power number calculated from Encounter
(automatically generated by Encounter.)  Encounter's power analysis can
handle a netlist with clocks inserted or not. Its accuracy is highly
dependant on usage model, more accurate information yields, understandably,
more accurate power analysis.


> Ring macros and other special cases: SE Sroute does a decent job of
> connecting row metal to ring macros (e.g., RAMs, register files) in most
> cases but coughs sometimes where high congestion exists.  (For example,
> where a via was dropped to get from the macro's internal supply to the
> ring around the macro.)  Unfortunately, this happened often enough that
> we couldn't ignore it, so more hand fixing.  How is FE with this today,
> as I understand it uses a new version of SE's Sroute for most heavy
> lifting?
>
>     - Mark Wroblewski
>       ex-Cirrus and looking                      Lafayette, CO


Although the Silicon Ensemble did not support Ring macros, SoC Encounter
is capable of hooking up special case macros including Ring Macro's.  The
recipe for hooking this up is highly design dependent.

Example script for Ring macro connection:

  connectBlockPin -selected 1 -ringPinTopBottomMinWidth 8 
          -ringPinLeftRightMinWidth 8 -ringPinTopBottomLayer metal1 
          -ringPinTopBottomMaxWidth 16 -ringPinLeftRightMaxWidth 16 
          -ringPinMaxConnections 500 -nets {VSS VDD} 
          -ringPinLeftRightLayer metal2

Hope this helps your readers, John.

    - Steve Cline
      Cadence                                    Austin, TX


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