( ESNUG 412 Item 10 ) ------------------------------------------- [05/22/03]
Subject: ( SNUG 03 #10 ) Pallab Discusses Power Compiler's Practical Limits
> Session 2 10:45 - 12:00 - Leakage Power Optimization Using Power Compiler
> and Multi-Threshold CMOS Technologies
>
> Basic idea is to compile the design with a mixture of high and low Vt
> cells. Low Vt have higher leakage than high Vt. Low Vt (fast) cells for
> critical paths, and High Vt (slow) cells for non-critical paths. Power
> Compiler would do that for us (ain't nice this Power Compiler?)
>
> Then he goes into several benchmarks to show the reduction on leakage.
> None of the benchmarks are convincing, as they have flaws in their basic
> assumptions.
>
> Q. Does PhysOpt optimize timing, and it forgets about power-optimizing
> non-critical cells?
> A. Let's discuss that off-line
>
> Lots of questions in this session. Mostly shows that Synopsys didn't make
> a good case here."
>
> - Santiago Fernandez-Gomez
> Pixim, Inc.
From: Pallab Chatterjee <pallabc=the_one the_many=siliconmap.net>
Hi, John,
I have not used Power Compiler but I have been doing Low Power RF and Mixed
Signal design for 20+ years. I was at the SNUG'03 Power Compiler tutorial
and it was pretty brutal to the speaker. The audience was very vocal about
some short comings on the tools, its performance and integration into flows.
1. The test results of their design in the 1200-2500 gates range is NOT
sufficiently large to be extrapolated to the 500K-1M gate design that
were of interest.
2. Their test design with a tight power constraint took aver 30 min to run
(2K gates) -- these runtime numbers are not acceptable for large
designs using Power Compiler. 100 k gates taking 25 hours?
3. In the slides for the architecture of mixed Vt cells (High VT device
between a high speed low VT device and power), Synopsys is advocating
power management in a style derivative of the Eric Vittoz approach for
sample data power. This is OK if you understand the following side
effects:
* You have major SI issues as the high VT device has to be driven
VERY hard to be able to initialize the power path for low VT logic.
This forms a strong multi-net aggressor net that has a fairly
significant settling time and can cause quite a mess in high
speed paths.
* Most of the existing standard cells do NOT have sufficient CMRR and
PSRR to be able to support the offset of the series device without
full re-characterization & modification of the switching waveforms.
Most complex gates can no longer be described with simple liberty
models due to the variability of the waveforms and require SPDM
models.
* There are several physical design issues with these series device
and their inherent routability for signal drive and power route.
* These multi-VT gates and the associated control signals are not
generally supported by DFT and clock tree tools.
4. The operation mode dynamic power does not seem to scale in a correlated
fashion with the results for the leakage power optimization, so lots
of post layout analysis was required with Power Compiler output.
5. If the design has multiple power supplies (typical for modern UDSM
technologies) the analysis would produce results that are almost too
complex to analyze in a finite period of time.
As a results of these 5 high level items, I do not think, at this time, that
Power Compiler is applicable as the solution of the automated leakage power
reduction. The interface of the tool into a flow isn't quite ready. A more
practical solution is the the standard practice of sampling data power
supply modulation for the control of these blocks. These standard solutions
can be modeled and signed off using traditional high capacity/mixed mode
simulation.
- Pallab Chatterjee
SiliconMap, LLC Livermore, CA
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