( ESNUG 406 Item 12 ) ------------------------------------------- [02/12/03]
Subject: ( ESNUG 404 #16 ) Better DC/PhysOpt Results With 0 Wireload Models
> Further experimentation after tapeout found that we could reduce the
> area of some blocks even further by not using any wireload models during
> DC synthesis, just fanout rules and reduced cycle times to get the faster
> architectures, and then letting Dolphin do the appropriate logic mapping
> and sizing. The savings were on the order of 10% for a one million gate
> block.
>
> - Tim Lantz
> Tau Networks Scotts Valley, CA
> PhysOpt is good, but it would be great if the buffering removal
> capabilities in PhysOpt were better. We realized a 10-15% timing and
> area savings when going from gates-to-placed-gates if we compiled with
> 0 wireload and fast timing, as PhysOpt just added more buffering to the
> already buffered paths instead of ripping or upsizing.
>
> - Gregg Lahti
> Corrent Corp. Tempe, AZ
From: Benny Winefeld <sock=benny dresserdrawer=mondes tot lawn>
Hi John,
Two comments in ESNUG 404 caught my interest and I wanted to draw your
readers attention to them. Both Tim Lantz and Gregg Lahti have seen a
benefit from using a zero wireload model with tightened timing
constraints to encourage DC to produce a design that is more suitable
for physical synthesis downstream. We have independently found that
same strategy at Monterey and it works pretty well in most cases. The
tighter clock cycles seem to encourage synthesis tools to pick faster
architectures (just be sure to restore your actual timing constraints
before entering into physical synthesis.) Using zero wireload models
keeps synthesis from wasting time on pointless buffering and sizing.
As you know, statistical wireload models are practically useless with
modern processes -- wire delay has become so significant that it needs to
be modeled accurately during optimization. In our experiments we've
found that the improvements in timing achieved during tech mapping using
non-zero wire load models are largely illusory and are not reflected in
the final timing achieved after physical synthesis, during which 80% or
more of the gates are changed anyway. By contrast, choices made during
architecture selection are extremely important to the final timing of
the circuit.
We've embodied the above strategy directly in our Dolphin-RTL product,
but your readers may want to experiment with this approach with whatever
tools they are currently using. It is likely to help, as Tim and Gregg
have both found.
- Benny Winefeld
Monterey Design Systems Sunnyvale, CA
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