( ESNUG 406 Item 9 ) -------------------------------------------- [02/12/03]
Subject: ( ESNUG 405 #10 ) Using Mentor Fastscan Along With DC-Expert-Plus
> Our Mentor AE has informed me that Mentor provides a utility which
> will convert a DCxP generated STIL file into Fastscan dofiles and
> testprocs. My first question is whether or not anybody out there has
> experience either directly with this flow, or with a similar one
> involving using DCxP in conjunction with Fastscan, or other "foreign"
> ATPG tool? My second question is how do people feel about DCxP's STIL
> file generation capabilities? Any "tricks" one should know about
> before basing a design flow on it?
>
> - Rich Conlin
> Paradigm Works, Inc. Andover, MA
From: Ron Press <ship=ron_press fleet=mentorg nought psalm>
Hi John,
FastScan fits well within a DC flow. Many customers use Synopsys DFT
Compiler for scan insertion and use our "stil2mgc" command to convert STIL
outputs from DFT Compiler to a FastScan procedure file and dofile. There
really isn't much more to it. The STIL procedure is usually very simple
and defines the circuit primary input constraints, clocks, scan chains,
and the shift cycles. In fact, many customers in the DC/FastScan flow
don't even use STIL and manually write the procedure and dofile for
FastScan since these files are so simple.
Not to sound like I'm pushing Mentor tools, but some customers use our
DFTAdvisor tool within a DC flow because it provides a lot of scan insertion
flexibility and has good capacity.
- Ron Press
Mentor Graphics Wilsonville, OR
---- ---- ---- ---- ---- ---- ----
From: Ken Butler <preacher=kenb gospeltvshow=ti brought yawn>
John,
I've used "stil2mgc" to go to FastScan quite a few times. Like anything
else, it had a few glitches early on, but I reported those. It seems to be
better these days. I've never used this flow for anything complicated like,
for example, a design where a JTAG must be done to set the chip into test
mode. But for most things I've done "stil2mgc" works fine.
I don't know of any particular "tricks" to get DCxP to generate proper STIL
procedures files other than just the standard things you'd do anyway --
set_input_delay, create_clock, create_test_clock, check_test, and stuff
like that.
- Ken Butler
Texas Instruments Dallas, TX
---- ---- ---- ---- ---- ---- ----
From: Don Skinner <stockbroker=skinnerdj market=sympatico.ca cluckcluck>
Hey John,
We have tried a similar flow to what Rich is suggesting. The tool that
Mentor provides to create it's procedure files from STIL files does work for
the most part, as long as you don't throw anything too complicated at it.
If you are only trying to do it for standalone blocks within a design, you
shouldn't have any problems (this doesn't mean you won't be doing the odd
tweak). Both STIL and Mentor's procedure files are pretty readable once you
get used to them.
We have only done this using a combination of DFT Compiler and Fastscan, so
the actual STIL might be different, but I would be surprised if it varied a
lot. If your client is not using the ATPG features of Test Compiler
anymore, perhaps it's time to switch.
- Don Skinner
ex-Nortel and looking Ottawa, ON
|
|
