( ESNUG 406 Item 8 ) -------------------------------------------- [02/12/03]
From: Steve Hoeft <bee=steve.hoeft hive=synopsys caught qualm>
Subject: Synopsys Warns That You *MUST* Use The change_names Command Now!
Hi John,
I am an Synopsys AC in Mountain View and I thought the following would be
useful to the ESNUG readers. It will be a SolvNET article soon, but a
wider distribution is even better.
You should always use "change_names" in your design flow. Do not rely on
"write Verilog" or "write VHDL" to change your design names.
The change_names command will continue to be developed. Write Verilog and
write VHDL will not have bug fixes done to their under the hood name
changing code. This applies if you are passing information between Synopsys
tools using ANY format other than a Synopsys design DB or Milkyway.
Now, you might ask "Why not do the changes under the hood when writing
out the files?"
Doing under the hood changes is not a good thing to do precisely because
it is done under the hood. If there is a problem you have no recovery
method. Additionally, it still means that your design DB and the output
files are out of SYNC!!! By having a central name change command or
commands you can ensure that the changes were correctly and fully done
before saving any data to disk. This is safer than making under the hood
changes.
In the 2003.03 release the current Verilog and VHDL writers apply under the
hood changes if the design DB contains non-compliant names. This has been
their behavior for years and you do not need to worry about existing scripts
or flows. If you have already applied "change_names -rules verilog -hier"
or "change_names -rules vhdl -hier" the writers do not need to make any
changes because the design is already name compliant with your chosen output
format. If you are not applying "change_names" as part of your existing
flow, you should add this now. It will make your flow much more robust now
and in the future.
In the future, the writers will assume that "change_names" is doing all the
necessary changes and will stop making under the hood changes. This is to
avoid duplication of code and duplication of capabilities that are not quite
100% exactly the same. It will also remove the side effect of under the
hood name changes that can cause difficulties when trying to debug design
and netlist inconsistencies.
So, the simple message is:
After ANY design change use the change_names command before you save any
files to disk!
This will ensure that your design DB and any subsequent file formats, and
reports, are consistent with each other and have no naming issues. If your
scripts do not have "change_names -rules Verilog/VHDL -hier" in them, add
it now.
- Steve Hoeft
Synopsys, Inc. Mountain View, CA
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