( ESNUG 403 Item 14 ) -------------------------------------------- [11/20/02]
From: Jia Di <mrjiadi inside of hotmail|liamtoh lot mom catcatcat>
Subject: Customer Runs Into Newbie PowerMill Problems; Seeks Others Help
Hi, John,
I just started to use PowerMill for quick power simulation. I have two
problems on it:
1. When I tried to simulate a design, PowerMill asked me to provide SPICE
netlist of ALL modules used in my design. All my designs are written
in VHDL and synthesized by Synopsys Design Compiler/Analyzer. Then
they are saved in Verilog format. After converting to EPIC using
Vlog2e, these designs contain only Synopsys standard gates like AO5 and
EO1, etc. I think PowerMill should know what they are. But now I have
to provide the netlist of even AN2. Is there another way to do this?
It is hard to provide all of them because the libraries of Synopsys
are un-readable.
2. In simulating some designs, I got error message like "Bus error-Core
dumped". I have no idea of this error. I don't think its my design
that's causing this.
Any ideas, anyone?
- Jia Di
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