( ESNUG 401 Item 6 ) --------------------------------------------- [10/17/02]
From: Urban Jangren <urbanj@QThink.com>
Subject: We Found Verplex LEC Caught Some Errors That Formality Had Missed
Hi, John,
On a recent project we completed a 7 M gate design in 0.13u technology. The
front-end team used Formality for formal verification & during the back-end
work that I participated in we used Verplex LEC. I was surprised that we
uncovered some floating signals (inputs to an ARM core) in the netlist that
was not detected by Formality. I am not sure if this was an operator error
or a lack of capability in the tool, but it confirmed my belief that Verplex
is an easier tool to work with and it produces good results.
- Urban Jangren
QThink
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