( ESNUG 398 Item 4 ) --------------------------------------------- [07/31/02]
Subject: ( ESNUG 395 #10 ) Here's The Cadence Tool Flows That Users Use Now
> I'm trying to get a complete Cadence-based tool flow up and I'm confused
> by Cadence's product line. In particular I'm referring to:
>
> Preview Silicon Ensemble
> DSM Silicon Ensemble
> PKS (aka Silicon Ensemble PKS)
> First Encounter
> SOC Encouter
>
> We don't have First Encounter, but we do have PKS 4.0, DSM SE 5.3, and
> Preview (IC446).
>
> All these tools have substantial overlap. It seems like Cadence is moving
> towards First Encounter and PKS as the complete solution. That's great for
> the future, but what about now? BTW, we use multiple power supplies on the
> chip (with inherited connections in Composer). How is the power
> connectivity information conveyed between this new mix of Cadence tools?
>
> - Albert Ma
> M.I.T. Cambridge, MA
From: Geoff Smith <gjsmith@cisco.com>
Hi, John,
Our working Cadence/Synopsys/Mentor flow is:
Virtuoso (IC446) (analog layout -> macrocells)
Ambit/Synopsys -> (rtl-to-gates) (Artisan libraries)
LogicVision (membist, scan, icBIST, bscan)
Silicon Ensemble (detailed floorplanning)
PKS (physical placement)
CTPKS (clock tree generation)
Silicon Ensemble (detailed route and 2.5D extract)
CeltIC - signal integrity
Virtuoso (IC446) for gds merge and manual fixes
Assura/Calibre for LVS/DRC
First Encounter is currently under eval for hierarchically partitioning
large designs (i.e. a better floorplanner).
- Geoff Smith
Cisco Systems Toowong, Australia
---- ---- ---- ---- ---- ---- ----
From: [ Barney, the Big Purple Dinosaur ]
Hi, John,
Albert has too many questions, which would need too much time to answer
them exactly.
1. FE & PKS IS NOW. We are already using it.
2. Take FE for the floorplan, power routing, initial placement, IPO
timing analysis, hierarchical partitioning (if applicable.)
BTW, SoC Encounter includes FE, PKS, CTS, CeltIC and SE-Ultra
router, which will be later replaced by Plato.
It is easy to use, all the technology and design data are in ASCII.
We like the hierarchical floorplanner and power routing. Also
initial placement is very good. No problem with a mixture of
custom blocks and SCells, we are doing also multiple power domains.
3. You have not mentioned all relevant tools which you would need to
complete your flow. On the other hand it is not clear what kind
of design (technology, complexity) are you going to do. Unfortunately
the problems are always hidden in a detailed application of the flow.
Best regards,
- [ Barney, the Big Purple Dinosaur ]
---- ---- ---- ---- ---- ---- ----
From: Rajesh Pathak <rpathak@cadence.com>
Hi John,
Any overlap between our tools is incidental as some tools were as a result
of aquisition. Suffice it to say that SOC Encounter is a grand integration
of SE-PKS, First Encounter (FE) and signal integrity tools like Celtic,
Simplex etc. FE is a silicon prototyping tool useful in a SOC environment
for legal placement of disperate blocks like IP, analog, memory, etc. This
legal placement frees a designer to concentrate on block level hardening
of these blocks from a chip level perspective. The global (chip level)
information like feed-thrus I/O constraints, placement obstructions like
global buffers etc are passed to the block level so that the blocks are
hardened in the context of top-level. At the block level, either SE-PKS or
FE is used to complete the block level P&R.
Since Albert is primarily interested in a flat design an appropriate tool
would be SE-PKS which he indicated he already has access to (PKS 4.0 and
Silicon Ensemble). SE-PKS is our tool of choice for timing critical
and congested designs.
One thing I am curious about is what does he mean by multiple voltages being
present in the design? Is he referring to voltage islands or that he has
library cells with multiple voltage rails? In both the cases I am afraid he
would be hitting a brick wall. Library formats like ALF or .lib does not
support multiple power supplies. One can fool the front-end engines like
static timing by manually editing the .lib file to reflect only one voltage
although the timing arcs have actually been characterized with more than one
(and different) voltage rails. However one would not find such luck with
back-end engines. OLA (open library acess) has been working on supporting
multiple voltages in the libray formats, but it is not out yet. FYI, PKS
will be supporting OLA in future.
Assuming he has one voltage rail (for the core) the methodology would be
fairly straight-forward. First he would have to extract a LEF from his
custom datapath block gdsII using Picasso/Abgen. Create a STAMP model or
TLF for the same block. He can use Pearl with the BuildTimingModel command
to create the TLF format. Once the physical abstract (LEF file) and timing
model (TLF or STAMP) has been created for this block, the block can then be
used as library macro in the flow. The flow sequence would be:
# Read Library
read_alf library.alf
read_tlf datapath.tlf
read_lef library.lef
read_lef_update datapath.lef
# Read top level RTL
read_ver {design.v ......}
# Elaborate
do_build_generic
# read synthesis constraints
source constraints.tcl
# create gate-level netlist
do_optimize
# read floorplan DEF. created using PKS or SE.
# This DEF has std cell rows and placed datapath macro (auto or
# manual)+IOs, core and block rings
read_def floorplan.def
# place std cells
do_place -timing_driven true
# Insert physical clock tree using a clock tree constraints file
source cts.tcl
do_build_clock_tree
# Run Timing
report_timing
do_xform_optimize_slack
do_place -timing_driven true
# Use SE to connect rings and follow pins for VDD and GND nets
# Global Route
do_route
# Repeat the following steps until timing convergence
do_xform_tcorr_ipo
# Final route
do_wroute
# extraction
do_hyperextract
# read extraction
read_spef
# timing analysis
report_timing
Go to back up to the step at "do_xform_tcorr_ipo" and repeat if your
timing is not met. Hope this helps.
- Rajesh Pathak
Cadence Design Systems Houston, TX
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