( ESNUG 398 Item 1 ) --------------------------------------------- [07/31/02]
Subject: ( SNUG 02 #19 ) A User Review Of Hidden Dragon / Floorplan Compiler
> Other than FPGAs, most of these wounded/dying Synopsys tools are playing
> in under $10 million markets. That is, they're mostly expendable
> experiments. If they succeed, great. If they fail, kill'm. Let the
> market decide. The only baby tool they can't ignore, though, is Hidden
> Dragon. In terms of future tools, Hidden Dragon (or something like it)
> must work.
>
> - from the SNUG'02 Trip Report
From: Valentina Baiardo <valentina.baiardo@st.com>
Hi John,
We just did an eval of the new Synopsys Floorplan Compiler (FPC) that your
readers may know as Hidden Dragon. Our goal was to find out if it was
better than our standard Chip Architect/PhysOpt flow. We were mostly
interested in its virtual flat approach to see if it could reduce the
amount of time required to create the final floorplan. Of particular
interest is how it handles hierarchy definition and block planning. Our
second objective was to evaluate its ability to analyze the power grid
at floorplan level.
To perform the evaluation we used two hierarchical designs.
Design 'Asterix' was a 1 M instance (~4 M gate) 0.18 um design with 10 top
level soft blocks and 16 embedded hard macros. At the top level, in
addition to the soft blocks it had over 3 K leaf cells and ~10K nets.
Asterix' highest system clock is 80 MHz.
We ran Floorplan Compiler virtual flat floorplanning on the Asterix gate
level netlist with cluster placement on all the soft blocks. It prooved
a very fast cycle time, half a day to obtain the top level floorplan with
results compatible with the final floorplan of the production design.
Compare this with the one week necessary for the original chip designer
to complete the floorplanning after the IO placement was frozen.
Design 'Obelix' was a 1.4 M instance 0.13 um design (~5.6 M gates) with 7
top level soft blocks, 35 K leaf cells and more than 230 embedded hard
macros. The top level of Obelix had more than 50K nets. It's highest
system frequency was 15O Mhz with the I/O frequency exceeding 600 MHz.
We used Floorplan Compiler in the real implementation flow to identify the
optimal top-level partitioning starting from an incomplete netlist where
a block (15% of the Obelix netlist) was missing.
While Asterix was done using the recommended top down virtual flat approach,
with Obelix we needed to apply both the top down and bottom up approach. We
created a bottom up floorplan for the most critical block whose frozen
floorplan was loaded using reload_subdesign. We set set_don't cluster to
true and set_shape constraints to rigid on this block and again ran cluster
placement on the full Obelix design. A keepout to reserve placement area
was added to mimic the presence of the missing block.
The floorplan completed with a very fast cycle time (10 minutes for cluster
creation and half an hour for cluster placement). The top-level
architecture was well understood and the blocks identified were successfully
closed in term of timing and routability in our Apollo back-end flow.
We experienced some issues in cluster legalization and floorplan creation
which are currently being worked on by the Synopsys product team. These
forced us to do minor manual optimizations to the floorplan to meet our
routability goals but this additional effort was only a few hours.
The secondary objective of our Floorplan Compiler eval was to test its newly
developed embedded power network analysis (PNA) capability. It promised
some interesting "what if" analysis capabilities. In addition it claimed to
have similar quality and correlated results with our signoff power analysis
tool, Simplex VoltageStorm GDSII.
The design we selected to test PNA on had 86 hard blocks, 1 IP core and 350 K
leaf cell instances. It only took 5 minutes for extraction and power network
analysis. The preliminary comparison showed a relative good match to Simplex
in the IR drop distribution. The colour maps generated looked similar to
VoltageStorm's analysis, with the observable differences accounted for in
the absolute value due to the missing IP block in the PNA data base.
Our eval has convinced us that Floorplan Compiler's virtual flat approach is
a significant value added to our design flow. As for bugs, the tool appears
mostly stable. Its hierarchy management and block planning features can
significantly improve design productivity and we found it reducing
floorplanning cycles from weeks to days. Our target for PNA adoption is
early Q4 2002.
- Valentina Baiardo
STMicroelectronics Agrate, Italy
|
|
