( ESNUG 396 Item 3 ) --------------------------------------------- [07/11/02]
Subject: ( ESNUG 395 #6 ) Aristo/SPC/PhysOpt Rectilinear Block Design Flows
> For our upcoming hierarchical design chip, I see that our blocks will be
> well utilized based on the connectivity and functionality -- if our blocks
> are allowed to be rectilinear (non rectangular) in shape -- rather than
> the conventional rectangular shapes. Even though the EDA tools out there
> claim that they can handle rectilinear shapes, I am very positive that I
> will run into a lot of implementation and integration issues in doing so.
> So I am wondering if your readers have experience in handling rectilinear
> blocks, especially with Synopsys (PhysOpt)/ Avanti (Jupiter/Apollo) tools.
>
> Some stuff that I am curious about are
>
> 1. How difficult is it in getting the pins assigned when the number of
> edges exceeds 4?
> 2. Is power routing capable of dropping straps of different lengths
> because of different dimensions in one direction or do I have to
> manually alter the lengths?
> 3. Will writing out the GDSII have any problems?
> 4. Can the parasitic extractor handle arbitrary shaped blocks?
>
> Plus is there anything else that would make my life miserable here?
>
> - Jay Pragasam
> Brecis Communications San Jose, CA
From: Anthony Galdes <anthony@mondes.com>
Hi John,
Rectilinear (L-shaped) blocks can be a real headache. The biggest problems
lie in two areas; design planning and block implementation.
- Inside the block, the area that's left for macro and cell placement might
be quite fragmented, so the utilization & congestion might not be great.
Depending on the nature of the problem, you can sometimes use the
mega-cells to mask some of the fragmentation by placing them in the
"alcove" areas and effectively reducing the number of edges of the
placeable standard cell area. It also helps to tune macro placement at
the chip-level rather than at the block level.
- At the chip-level the problems are a little tougher. The largest area of
concern is port placement. You'll need a tool that can place ports along
all 6, 8, 10... edges of your block. Doing this by hand isn't an option,
unless you have lots of time in your schedule. The port placement needs
to look into the block so that it doesn't create more headaches for the
guy implementing the block itself. Your planning tool will also need to
keep track of the power grid so that all the edges of the rectilinear
block synchronize with the top-level power mesh. If you keep track of
these issues, life shouldn't be too "miserable".
Our customers have been using Aristo IC Wizard to build designs w/ L-shaped
blocks for over two years. They don't seem to have problems interfacing
L-shaped blocks to Avanti Apollo. IC Wizard helps Cadence users by creating
overlap blockages for cutout areas when exporting DEF and also creating a
MAC (command script) file that SE uses to trim the rows as necessary.
So my vote? Go ahead and crank out that design with a couple of L-shaped
blocks.
- Anthony Galdes
Monterey Design Systems Sunnyvale, CA
---- ---- ---- ---- ---- ---- ----
From: Steve Cline <scline@cadence.com>
Hi, John,
Some PhysOpt/Apollo users use Cadence's First Encounter (FE) for rectilinear
partitions. FE allows you to select any module in the design hierarchy as
a partition. Once the decision has been made on which blocks to partition,
a typical sequence runs as follows:
1. Specify the module to be partitioned using the Partition -> Specify
Partition... menu. In the Specify Partition form, give the
hierarchical instance name and a partition name, and click on
Add/Replace to add the partition to the list of modules to be
partitioned. Clicking 'OK' will change the module 'guide' (FE-ese
for a non-exclusive placement area) to a 'fence' (FE-ese for
exclusive placement area). (Also make sure you check the "Save
Partition Spec to" button and give a filename which can be used
in the top-level reassembly process starting in step 7 below.)
2. Select the 'Add Partition Rectilinear Cut' Tools Widget.
3. Using the left mouse button draw the rectilinear cut(s) over the
existing rectangular module definition to create the rectilinear
shape desired.
4. 'Place' and 'Trial route' the design using the Place -> Place... and
Route -> Trial Route... menus respectively.
5. Create the block level partition using the Partition -> Partition...
menu, selecting the 'Perform Pin Assignment' button.
6. Save the partition data using the Partition -> Save Partition... menu.
Select the PDEF output format button if you are going into PhysOpt.
This will then save data into a directory with the partition name
given to the partition in step 2. This information can then be used
to complete the block-level design. There will be a Verilog netlist
as well as a PDEF file which contains a definition of the rectilinear
region, including the pin assignments on the boundary, as well as
power busing pushed down from the top-level. Furthermore there will
be block-level timing constraints derived from the top-level timing
constraints that can be used to drive PhysOpt. These constraints are
based on the full-chip timing analysis done in FE and budgeted
accordingly. The pin assignments will be based on the actual routing
done in step 5. Note that the user has control to guide pin
assignments if desired, including putting in pin placement blockages.
All this data is used as the source for the PhysOpt run.
Once you have done the block-level implementation in PhysOpt, your block-
level design data can be read back into FE for further top-level analysis
and/or floorplan refinement using the following steps:
7. Re-import the design into FE using the new Verilog netlists. One of
the features of FE when partitioning is to also create a "top-level
partition" which includes a top-level Verilog netlist which includes
abstract instantiations for the partitioned modules. (Note that the
top-level partition directory also allows top-level hierarchical
optimization using both abstract timing (ILM, Stamp) and physical
(LEF for example) views for the partitioned blocks.) This netlist can
be read into FE along with the updated block-level Verilog netlists
to create a description of the newly optimized hierarchical design.
The FE Design Import form in the GUI allows navigating to find and
select the updated Verilog netlists.
8. Reload the original top-level floorplan.
9. Reload the partitions. This is done using the Partition -> Specify
Partition... menu and then clicking the Load... button and loading the
partition spec file saved in step 1 above.
10. Repartition the design using the Partition -> Partition... menu. Don't
do pin assignment.
For each partitioned module, do the following:
11. Select the partitioned block in the FE GUI.
12. Do Partition -> Change Partition View. This will push down into that
block.
13. Load the placement and/or routing data for that block using either the
Place -> Load Place... or Route -> Load Route... menu. This will allow
you to load place/route data from your block-level tool using PDEF or
other formats.
After doing steps 11-13 for each partitioned block:
14. Partition -> Unpartition... selecting all modules to be unpartitioned.
At this point you will have all of the detailed block-level place/route
data loaded back into FE and stitched together. You can then run
full-chip timing analysis, and IPO if necessary. Furthermore, if your
timing is still not being met at this point, you can refine your
floorplan and repartition (for example getting more refined block-level
timing budgets/constraints) based on this updated data.
There are several steps in this process, but in practice the whole sequence
runs fast and is pretty easy to use; and offers a number of advantages in
terms of accurate partitioning, timing and congestion analysis, etc.
- Steve Cline, FE FAE
Cadence Santa Clara, CA
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