( ESNUG 395 Item 5 ) --------------------------------------------- [06/26/02]
From: Wayne Miller <Wayne.A.Miller@smsc.com>
Subject: Should DC Buffer Up 40 Fanout Nets Or Should Backend Tools Do It?
Hi John,
I'm looking for a guideline and/or experiences for large blocks or small
chips on when to allow Design Compiler to buffer high fanout nets, versus
having your physical tool insert a buffer tree later in the design flow.
In other words, if a net has 40 loads, should the Design Compiler be
allowed to buffer the net, or should it be classed as an ideal_net? What
about 100 loads? 200 loads? Obviously these aren't clocks, nor a master
scan test enable that goes to every flop. These are nets in the grey area
in between. We've had some congestion problems with an internal reset
that had a large fanout. It was an easy fix to have layout insert a
buffer tree, but the question came back as to what threshold should
be used.
- Wayne Miller
Standard Microsystems Corporation
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