( ESNUG 395 Item 4 ) --------------------------------------------- [06/26/02]
From: Himanshu Bhatnagar <himanshu.bhatnagar@conexant.com>
Subject: DC's Renaming Of Nets Troublesome With Verilog Gate Simulations
Hi John,
We are running into problems with respect to gate level sims. The Verilog
netlist produced by Design Compiler optimizes the net names and they become
"n1234" or something like that. Our testbenches probe the internal nets and
therefore it becomes increasingly difficult to map the RTL signal names to
gate level signal names. I was wondering if there is a variable in Synopsys
that controls the outcome of the signal names? In other words, how can
preserve the RTL signal names in DC netlists?
- Himanshu Bhatnagar
Conexant Systems, Inc.
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