( ESNUG 393 Item 12 ) -------------------------------------------- [04/25/02]
Subject: LEF & Verilog Won't Do; Hard Macros In PKS Need A TLF Or ALF File
> I'm trying to use PKS to synthesize and P&R a semi-custom design. I have
> datapath hard-macros which I have created LEF abstracts of. The control
> logic is in Verilog. The design hierarchy is also in Verilog. What I
> want to do is to manually place all the hard-macros and then do a flat
> synthesis/P&R from the top-level. Has anybody done this before and have
> any insight into this?
>
> One problem I'm getting is port ordering. When a macro is instantiated in
> Verilog, how does it know which port is which? I tried created a dummy
> Verilog block for the datapath macro with only the ports defined. Didn't
> work. I think it thought the block was empty. Will port connection
> by name solve the problem?
>
> PKS doesn't seem to be doing anything with the LEF files I'm importing.
> It keeps complaining that there is no physical information about the
> blocks. Am I doing something wrong?
>
> - Albert Ma
> MIT Cambridge, MA
From: Christopher Van Beek <cv74215@attbi.com>
I'm unemployed and haven't touched PKS is months, but here is what I
remember. By the way, if anyone is hiring in the Portland, Oregon area,
let me know.
I think the problem you are having is during the technology mapping phase.
Do you get warnings about block boxes being created, or that the design
has black boxes?
The only time I have had port ordering problems is when I let Ambit/PKS
create a block box for a macro and then saved the database (.db). Then in
a new session, I loaded the real library file (.alf) for the hard-macros
and reloaded the saved database. This gave me errors. The pin order for
the auto-created library abstract did not match the "real" one I loaded
later.
I think all you have to do is read in the library abstract (.alf) for the
hard-macro when you first synthesize. I used to read in the standard cell
library and then a bunch of abstracts for RAMs before any synthesizing.
Also, make sure you set the global variable which tells which libraries to
use during technology mapping to include all the libraries. You should not
get any warnings about black boxes.
There might be ways to auto-generate an alf/lib file in SE, but I have never
done that. I know our RAM compiler would spit out a .lib file which
'libcompile'-d to .alf quite nicely. There might be a way to do it with
.tlf files, but I have not done that, either. If you are stuck, I guess you
could manually create a .lib file. I don't think the timing info is
required, unless you want to do timing analysis in PKS or do timing driven
placement.
To control the placement of the hard-macros, you just have to pre-place them
in the floorplan DEF file you read into PKS. The only trick is to make sure
the instance names match exactly what the names will be when qplace is run.
It is easy to get caught double instantiating these cells if you change the
flattening of the design (ie. design has "top/middle/bottom/cell_instA" and
DEF file has "top_middle_bottom_cell_instA" - these don't match, so qplace
will place another instance and ignore the pre-placed one.)
- Christopher Van Beek Portland, OR
---- ---- ---- ---- ---- ---- ----
From: Albert Ma <ama@cag.lcs.mit.edu>
Thanks Chris,
Yup, I get black box warnings (when I don't read in a Verilog shell). So
PKS will not be happy until it gets a tlf or alf? I guess that's the
problem. I've been trying to get away without doing that. I was hoping
that it would intuit the info from a DEF and/or Verilog shell.
We have most of the Synopsys, EPIC, and Cadence tools. Anybody know if
there's a tool in there to autogenerate .lib or .tlf?
- Albert Ma
MIT Cambridge, MA
---- ---- ---- ---- ---- ---- ----
> One problem I'm getting is port ordering. When a macro is instantiated in
> verilog, how does it know which port is which? I tried created a dummy
> verilog block for the datapath macro with only the ports defined. This
> didn't work. I think it thought the block was empty. Will port
> connection by name solve the problem?
From: Robert Szczygiel <Robert.Szczygiel@cern.ch>
The instantiatied macro conectivity can be defined in two ways:
1.) By port order
nand n1 (net1,net2,net3);
The connectivity is determined by the port order. If the nand is
defined:
module nand(y,a,b)
then net1 is connected to y, net2 -> a, net3->b.
2.) By port name
nand n2 (.a(net1),.b(net2),.y(net3));
This is explicit, and does not depend on the port sequence in the
module definition.
Usually the tool which generates the netlist has some switches to choose
between the two modes. I have never used PKS, but Silicon Ensemble needs
to have an empty Verilog models for the macro blocks (and TLF, of course.)
- Robert Szczygiel
CERN Switzerland
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