( ESNUG 392 Item 5 ) --------------------------------------------- [04/18/02]
Subject: Synopsys R&D Q&A To The SNUG'02 ACS Tutorial (Day 1)
43. If I run acs_compile_design followed by acs_refine_design and then I
modify one of the blocks, do I need to recompile the entire design?
No. Each of the three compile commands has an -update switch that
allows you to specify a list of designs to update. When you set this
switch, Automated Chip Synthesis recompiles only the designs you
specify and their parent designs.
44. How does Automated Chip Synthesis handle include file dependencies?
In version 2002.05, the Automated Chip Synthesis front end has been
enhanced to recognize and include file dependencies.
45. Does Automated Chip Synthesis support mixed Verilog and VHDL source
files?
The acs_read_hdl command requires that all source files use the same
format. If your design has both Verilog and VHDL source files,
analyze the designs by running acs_read_hdl twice, once for the
Verilog files and once for the VHDL files. When you have mixed-format
RTL source files, you must manually elaborate the designs.
46. Can you control multiple jobs on a single machine and/or across
multiple hosts?
You can control multiple jobs on a single host with multiple CPUs by
using the acs_num_parallel_jobs variable. If you want to run across
multiple hosts, you must use GRD or Load Sharing Facility (LSF). The
way to use LSF with Automated Chip Synthesis is described in the
Automated Chip Synthesis User Guide, and the way to use GRD is
described in SolvIt article 903410.
47. I've noticed that the Design Compiler budgeter uses 8G of memory on a
400K design, versus 1G with the PrimeTime budgeter. Is this normal?
No. Design Compiler budgeter offers many advantages for synthesis
(faster, accuracy, RTL budgeting, and so on). However, it might
require more memory for some designs. For large designs a 50 percent
increase in memory might be normal, but an 8x increase is definitely
not normal and should be reported.
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