( ESNUG 389 Item 3 ) --------------------------------------------- [03/06/02]
Subject: ( ESNUG 388 #1 ) Dan Sees Synopsys As Hand Waving On C-Level Issue
> We will support C-Level's CycleC methodology by enhancing Synopsys'
> VCS' DirectC to support C-Level's restricted C/C++ coding style
> for simulation performance. ... DirectC, which provides faster RTL
> simulation, will compliment our CoCentric Studio SystemC simulator,
> which provides faster architectural and HW/SW simulation.
>
> - Mark Hartoog
> Synopsys, Inc.
From: Dan Joyce <dan.joyce@compaq.com>
Hi, John,
This answer sounds like hand waving to me.
I can not tell if Synopsys plans to:
a) Sell a new C++ simulator that reaches performance on the scale of
C-Level. (I certainly hope that they don't think SystemC can do
this. It can't.)
or
b) Reverse engineer C-Level's tool and use the information to improve
VCS and DirectC.
My concern is they will only do b) and continue to claim that SystemC is
still the C++ solution; using C-Level technology just for Verilog tool
improvement.
Our experience with C-Level was that the C-Level C++ HDL simulated so
much faster than Verilog, that having ANY Verilog in the design reduced
the simulation speed to nearly Verilog speeds.
Let me be clear -- SystemC is NOT the answer. SystemC performance is
around 1/1000 the performance we were getting with C-Level style C++.
SystemC is not much better than VCS - if that. If you are going to
create a new language, which Synopsys did with SystemC, why not address
the simulation speed issue?
- Dan Joyce
Compaq Austin, TX
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