( ESNUG 388 Item 8 ) --------------------------------------------- [02/27/02]
From: "Suttinan Chattong" <suttinan@cyberway.com.sg>
Subject: Can Cadence's CTGEN Generate A Viable Clock Tree For This Design?
Dear John,
I'm just wondering if anyone in ESNUG has experience working with Cadence's
CTGEN (clock tree synthesis tool) in Silicon Ensemble.
I have a design with complexity of about 500 K gates, 0.25 um technology.
The largest clock domain (100 MHz) has around 9,000 flip-flops connected
to it, and clock skew requirement for that domain is 0.25 ns (this number
was obtained from post-synthesis STA. Does anyone know if such a skew
requirement is achievable by CTGEN?
If anyone has prior experience about any other clock tree synthesis tool,
I would like to hear some comments about them - whether such a skew number
is achievable by anyone's state-of-the-art CTS.
Thanks in advance. :)
- Suttinan Chattong
Centre For Wireless Communications Singapore
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