( ESNUG 388 Item 5 ) --------------------------------------------- [02/27/02]
Subject: ( ESNUG 387 #3 ) Formality 2002.03 (Beta) Finds PhyOpt Buffer Bug
> One of the ACs in San Diego told me about a situation where PhysOpt can
> put "extra inversions" in your netlist and create bad logic. This
> problem can occur if your library has certain cell that can act as *both*
> a buffer and an inverter.
>
> - Mike Montana
> Synopsys, Inc. Dallas, TX
From: [ The French Olympic Skating Judge ]
Hi, John,
I must be anon here. Company politics.
We also encountered that PhysOpt bad logic bug in one of our designs using
Formality while running an RTL-to-synthesized-netlist check. But we were
in trouble. Formality 2000.05-FM.2 couldn't isolate the error due to the
size and complexity of our logic cone.
Our design was 60 K gates, ~310 Mhz, 0.18 TSMC. We were using PhysOpt
v2001.08-1. It turns out that during synthesis set_boundary_optimization
introduced an extra inversion in one path.
We decided to try the Beta version of Formality 2002.03. (It's supposed to
have larger capacity.) It pinpointed exactly where the problem was in our
synthesized netlist. Once we identified the problem and the net where the
change was needed, its new "Source Links" feature showed us exactly where
our Verilog source code needed to change.
We then quickly implemented and verified the fix by running another complete
RTL-to-Synthesized-Netlist check. I strongly recommend using Beta Formality
2002.03, if you can get it from Synopsys. At one point, we were afraid
we would have to re-synthesize this entire (very complex) design. That
would have taken 2 days when you consider that you'd have to restitch the
scan chain back into the new netlist plus redoing all the backend stuff.
Instead, our problem was completely resolved in a matter of hours.
- [ The French Olympic Skating Judge ]
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